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ADIN2111BCPZ-R7 Datasheet(PDF) 86 Page - Analog Devices

Part # ADIN2111BCPZ-R7
Description  Low Complexity, 2-Port Ethernet Switch with Integrated 10BASE-T1L PHYs
PDF  129 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADIN2111BCPZ-R7 Datasheet(HTML) 86 Page - Analog Devices

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Data Sheet
ADIN2111
REGISTERS
analog.com
Rev. A | 86 of 129
Table 146. Bit Descriptions for P2_RX_MIN_LEN
Bits
Bit Name
Description
Reset
Access
[31:16]
RESERVED
Reserved.
0x0
R
[15:0]
P2_MIN_FRM_LEN
Minimum Frame Length on Receive in Bytes.
0x40
R/W
P2 Rx Low Priority FIFO Frame Count Register
Address: 0xE8, Reset: 0x00000000, Name: P2_LO_RFC
The number of frames in the receive FIFO.
Table 147. Bit Descriptions for P2_LO_RFC
Bits
Bit Name
Description
Reset
Access
[31:9]
RESERVED
Reserved.
0x0
R
[8:0]
P2_LO_RFC
Receive Frame Count for the Low Priority FIFO. The number of frames in the Rx FIFO. Provided for debug
purposes. In store and forward mode, the host software only needs to know that there is at least one frame
available. See P2_RX_RDY.
0x0
R
P2 Rx High Priority FIFO Frame Count Register
Address: 0xE9, Reset: 0x00000000, Name: P2_HI_RFC
The number of frames in the receive FIFO.
Table 148. Bit Descriptions for P2_HI_RFC
Bits
Bit Name
Description
Reset
Access
[31:9]
RESERVED
Reserved.
0x0
R
[8:0]
P2_HI_RFC
Receive Frame Count for the High Priority FIFO. The number of frames in the Rx FIFO. Provided for debug
purposes. In store and forward mode, the host software only needs to know that there is at least one frame
available. See P2_RX_RDY.
0x0
R
P2 Low Priority Rx FIFO Valid Half Words Register
Address: 0xEA, Reset: 0x00000000, Name: P2_LO_RXSIZE
Number of valid half words (16 bits) in the low priority Rx FIFO.
Table 149. Bit Descriptions for P2_LO_RXSIZE
Bits
Bit Name
Description
Reset
Access
[31:14]
RESERVED
Reserved.
0x0
R
[13:0]
P2_LO_RXSIZE
Data in the Rx FIFO. Number of half words (16 bits).
0x0
R
P2 High Priority Rx FIFO Valid Half Words Register
Address: 0xEB, Reset: 0x00000000, Name: P2_HI_RXSIZE
Number of valid half words (16 bits) in the high priority Rx FIFO.
Table 150. Bit Descriptions for P2_HI_RXSIZE
Bits
Bit Name
Description
Reset
Access
[31:14]
RESERVED
Reserved.
0x0
R



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