AD538

Rev. E | Page 13 of 16

ANALOG COMPUTATION OF POWERS AND ROOTS

It is often necessary to raise the quotient of two input signals to

a power or take a root. This could be squaring, cubing, square

rooting or exponentiation to some noninteger power. Examples

include power series generation. With the AD538, only one or

two external resistors are required to set any desired power, over

the range of 0.2 to 5. Raising the basic quantity VZ/VX to a

power greater than one requires that the gain of the AD538’s log

ratio subtractor be increased, via an external resistor between

the A and D pins. Similarly, a voltage divider that attenuates the

log ratio output between Point B and Point C will program the

power to a value less than one.

3

12

18

17

2

10

15

8

RA

RB

RC

VO

VO

VZ

VY

VZ

VY

VREF

VX

VREF

VX

B

CA

D

POWERS

m

RA

2

196

Ω

3

97.6

Ω

4

64.9

Ω

5

48.7

Ω

3

12

2

10

15

8

B

C

ROOTS

m

RB

RC

1/2

100

Ω

100

Ω

1/3

100

Ω

49.9

Ω

1/4

150

Ω

49.9

Ω

1/5

162

Ω

40.2

Ω

RA =

RB = RC ≤ 200Ω

196

Ω

M – 1

VZ

VREF

VY (

) m

VZ

VREF

VY (

) m

=

–1

RB

RC

1

M

Figure 16. Basic Configurations and Transfer Functions for the AD538

SQUARE ROOT OPERATION

The explicit square root circuit of Figure 17 illustrates a precise

method for performing a real-time square root computation.

For added flexibility and accuracy, this circuit has a scale factor

adjustment.

The actual square rooting operation is performed in this circuit

by raising the quantity VZ/VX to the one-half power via the

resistor divider network consisting of resistors RB and RC. For

maximum linearity, the two resistors should be 1% (or better)

ratio-matched metal film types.

1 V scaling is achieved by dividing-down the 2 V reference

and applying approximately 1 V to both the VY and VX inputs.

In this circuit, the VX input is intentionally set low, to about

0.95 V, so that the VY input can be adjusted high, permitting

a ±5% scale factor trim. Using this trim scheme, the output

voltage will be within ±3 mV ± 0.2% of the ideal value over a

10 V to 1 mV input range (80 dB). For a decreased input dynamic

range of 10 mV to 10 V (60 dB) the error is even less; here the

output will be within ±2 mV ± 0.2% of the ideal value. The

bandwidth of the AD538 square root circuit is approximately

280 kHz with a 1 V p-p sine wave with a +2 V dc offset.

This basic circuit may also be used to compute the cube, fourth

or fifth roots of an input waveform. All that is required for a

given root is that the correct ratio of resistors, RC and RB, be

selected such that their sum is between 150 Ω and 200 Ω.

The optional absolute value circuit shown preceding the AD538

allows the use of bipolar input voltages. Only one op amp is

required for the absolute value function because the IZ input of

the AD538 functions as a summing junction. If it is necessary to

preserve the sign of the input voltage, the polarity of the op amp

output may be sensed and used after the computation to switch

the sign bit of a DVM chip.