MSC7119 datasheet(19/56 Pages) FREESCALE

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Electrical Characteristics

MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6

Freescale Semiconductor

2.3

Thermal Characteristics

Table 4 describes thermal characteristics of the MSC7119 for the MAP-BGA package.

Section 3.1, Thermal Design Considerations explains these characteristics in detail.

2.4

DC Electrical Characteristics

This section describes the DC electrical characteristics for the MSC7119.

Note:

The leakage current is measured for nominal voltage values must vary in the same direction (for example, both VDDIO

and VDDC vary by +2 percent or both vary by –2 percent).

Table 4. Thermal Characteristics for MAP-BGA Package

Characteristic

Symbol

MAP-BGA 17

× 17 mm5

Unit

Natural

Convection

200 ft/min

(1 m/s) airflow

Junction-to-ambient1, 2

RθJA

°C/W

Junction-to-ambient, four-layer board1, 3

RθJA

°C/W

Junction-to-board4

RθJB

°C/W

Junction-to-case5

RθJC

°C/W

Junction-to-package-top6

ΨJT

°C/W

Notes:

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on

the top surface of the board near the package.

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

Thermal characterization parameter indicating the temperature difference between package top and the junction temperature

per JEDEC JESD51-2.

Table 5. DC Electrical Characteristics

Characteristic

Symbol

Min

Typical

Max

Unit

Core and PLL voltage

VDDC

VDDPLL

1.14

1.2

1.26

DRAM interface I/O voltage1

VDDM

2.375

2.5

2.625

I/O voltage

VDDIO

3.135

3.3

3.465

DRAM interface I/O reference voltage2

VREF

0.49

× VDDM

1.25

0.51

× VDDM

DRAM interface I/O termination voltage3

VTT

VREF – 0.04

VREF

VREF + 0.04

Input high CLKIN voltage

VIHCLK

2.4

3.0

3.465

DRAM interface input high I/O voltage

VIHM

VREF + 0.28

VDDM

VDDM + 0.3

DRAM interface input low I/O voltage

VILM

–0.3

GND

VREF – 0.18

Input leakage current, VIN = VDDIO

IIN

–1.0

0.09

µA

VREF input leakage current

IVREF

——

µA

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