PS700 datasheet(25/38 Pages) MICROCHIP

25 / 38 page

 2004 Microchip Technology Inc.

DS21760F-page 25

PS700

4.4.16

OpMode – OPERATION MODE CONTROL REGISTER

OpMode: OPERATION MODE CONTROL REGISTER

(ADDRESS 7A HEX/DECIMAL 122)

SSLP

Reserved

SSLPdiv

Shelf

POR

sPOR

bit 7

bit 0

bit 7

SSLP: Sample-Sleep Enable bit

Setting this bit to a ‘1’ immediately enables Sample-Sleep mode. The low-power oscillator is

enabled and the A/D sampling rate is reduced. Clearing this bit to ‘0’ disables Sample-Sleep

mode.

= Sample-Sleep mode enabled

= Sample-Sleep mode disabled

bit 6

Reserved: Reserved bit location

bit 5-3

SSLPdiv: Sample-Sleep Divider bits

These bits set the interval between sampling of the A/D during Sample-Sleep. The timing is set

as: Sampling Interval = (.5 sec * 2 ** Sampdiv * 2 ** SSLPdiv)

bit 2

SHELF: Shelf-Sleep Enable bit

Writing a ‘1’ to this register will place the device in Shelf-Sleep mode. Volatile memory will not

be maintained. The Shelf-Sleep mode will not actually be entered until a SMBus Stop condition

occurs and then SDA and SCL go low.

bit 1

POR: Power-on Reset bit

A ‘1’ in this register indicates that a Power-on Reset has occurred. Write this register to ‘0’ to

clear this indicator.

bit 0

sPOR: Soft Power-on Reset bit

Writing a ‘1’ to this register will cause the device to re-initialize by writing the contents of the

EEPROM into all working registers.

Legend:

‘1’ = Bit is set

‘0’ = Bit is cleared

R = Reserved bit

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