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UPD8821 Datasheet(PDF) 6 Page - NEC |
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UPD8821 Datasheet(HTML) 6 Page - NEC |
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6 / 24 page ![]() 6 μ PD8821 Data Sheet S17961EJ2V0DS INPUT PIN CAPACITANCE (TA = +25°C, VOD = +10 V) Parameter Symbol Pin Pin No MIN. TYP. MAX. Unit φ1AO 10 235 260 285 pF φ1BO 32 235 260 285 pF φ1A 15 235 260 285 pF Cφ 1 φ1B 25 235 260 285 pF φ2AO 31 235 260 285 pF φ2BO 9 235 260 285 pF φ2A 26 235 260 285 pF Shift register clock pin capacitance Note Cφ 2 φ2B 16 235 260 285 pF 7 4 5 6 pF Last stage shift register clock pin capacitance Cφ 2L φ2L 34 4 5 6 pF Reset gate clock pin capacitance Cφ R φR 6 11 12 13 pF Reset feed-through level clamp clock pin capacitance Cφ CP φCP 35 13 15 17 pF φTG1 24 190 210 230 pF φTG2 23 155 170 185 pF Transfer gate clock pin capacitance Cφ TG φTG3 17 155 170 185 pF Note Cφ 1, Cφ 2 are equivalent capacitance with driving device, including the co-capacitance between φ1 and φ2. Remark Pins 10, 15, 25 and 32 ( φ1), pins 9, 16, 26 and 31 (φ2), pins 7 and 34 (φ2L), are each connected inside of the device. |
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