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UPD8821 Datasheet(PDF) 9 Page - NEC |
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UPD8821 Datasheet(HTML) 9 Page - NEC |
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9 / 24 page ![]() 9 Data Sheet S17961EJ2V0DS μ PD8821 TIMING CHART 3 (Bit Clamp Mode, Line Clamp Mode) t16 t14 φCP φR 90% φTG 10% t2 t4 t3 10% 90% t17 t5 90% 10% φ1∗ 90% 90% t12 t13 90% 10% t1 t15 t8 t9 t10 10% Caution "10%" and "90%" define as the clock voltage with 5 Vp-p condition. i.e. "10%" shows 0.5 V, "90%" shows 4.5 V Symbol MIN. TYP. MAX. Unit t1, t5 100 300 1000 ns t2, t4 0 10 – ns t3 500 5000 20000 ns t6, t7 0 10 – ns t6L, t7L 0 3 – ns t8, t10 0 3 – ns t9 6 125 20000 ns t12, t14 0 3 – ns t13 8 125 20000 ns t15 −3 +250 +1000 ns t16 0 125 – ns t17 4 125 – ns t20 5 125 – ns |
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