TDA9150B datasheet(22/36 Pages) PHILIPS

22 / 36 page

July 1994

Philips Semiconductors

Preliminary speciﬁcation

Programmable deﬂection controller

TDA9150B

TIMING (PRESCALER OFF;fclk =fLLC WHERE fclk = INTERNAL CLOCK)

fLLC

line-locked clock frequency

6.2

−

15.5

MHz

line-locked clock frequency ratio

between fLLC and fH

H locked

428

432

H unlocked

−

433

−

line-locked clock frequency ratio

between fclk and fH

H locked

428

432

H unlocked

−

433

−

LLCS input voltage

−

8.8

VIL

LOW level input voltage (pin 5)

−−

1.5

VIH

HIGH level input voltage (pin 5)

3.5

−−

IIL

LOW level input current (pin 5)

V5 = VSSD

−−

−150

µA

IIH

HIGH level input current (pin 5)

V5 = VCC

−−

100

µA

Horizontal part

INPUT SIGNALS

HA (pin 13)

VIL

LOW level input voltage

−−

0.8

VIH

HIGH level input voltage

2.0

−−

I13

input current

V13 = 5.5 V

−10

−

+10

µA

rise time

−

⁄2tLLC

fall time

−

⁄2tLLC

tWH

pulse width HIGH

× tclk

−−

tWL

pulse width LOW

× tclk

−−

HFB (pin 1)

VPSL

phase slicing level

FBL = logic 0

3.7

3.9

4.1

FBL = logic 1

1.1

1.3

1.5

Vblank

blanking slicing level

0.1

0.2

input current

−10

−

+10

µA

Horizontal phase (delay centre ﬂyback pulse to leading edge of HA; where N = horizontal phase data)

control range

× tclk

N + (432

− K)

× tclk

number of steps

−

OUTPUT SIGNALS

HOUT (pin 20)

V20

output voltage

I20 = 0

−

VCC

VOL

LOW level output voltage

I20 = 10 mA

−−

0.5

I20

input current

output off

−10

−

+10

µA

duty factor

normal operation

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

TDA9150B Datasheet(PDF) 22 Page - NXP Semiconductors

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