HA16158P/FP

Rev.2.00 Jan 30, 2007 page 13 of 23

3. Soft Start Circuit (for PFC Control)

This function gradually increases the pulse width of the PFC-OUT pin from a 0% duty cycle at start-up to prevent a

sudden increase in the pulse width that may cause problems such as transient stress on external parts or overshoot of the

PFC output voltage (B+ voltage).

The soft start time can easily be set with a single external capacitance.

V_ramp

(internal signal)

PFC-SS

comp. out

(internal signal)

PFC-OUT

3.4V

V_PFC-SS

Figure 3

Soft start time tss-pfc is determined by PFC-SS pin connection capacitance Css-pfc and an internal constant, and can be

estimated using the equation shown below.

Soft start time tss-pfc is the time until the PFC-SS pin voltage reaches lower-end voltage 0.65 V of the IC-internal

RAMP voltage waveform after VREF starts up following UVLO release.

Soft start time tss-pfc when Css-pfc is 3.3 nF is given by the following equation.

tss-pfc =

* Iss-pfc: PFC-SS pin sink current, 25

µA typ.

≈ 5.7 [ms]

=

Css-pfc

× (VREF − Vramp-L)

Iss-pwm

33 [nF]

× (5 − 0.65)

25 [

µA]

In addition, when you do not use a soft start function, please ground this terminal.