TEA1069 datasheet(15/44 Pages) PHILIPS

15 / 44 page

1998 Jan 08

Philips Semiconductors

Product speciﬁcation

Versatile speech/dialler/ringer with

music-on-hold

TEA1069; TEA1069A

Fig.12 Ringer frequency detection.

handbook, full pagewidth

CE/FDI

TONE

MBH200

VDD

VEE

sample

time

ringer response delay

(

<1.5 frequency cycle)

sync

time

In case of a valid ringer signal the user is alerted through

a melody at the TONE output, generated by the ringer part

of the TEA1069 and TEA1069A. This melody follows the

cadence of the ringer signal. Both the melody and the

volume can be selected. The melody frequency and

duration are given in Table 2.

Table 2

Ringer melodies

CRADLE SWITCH INPUT: PIN CSI

To distinguish among different operating states after

CE/FDI is activated, input CSI is used. The basic states

are shown in Table 3.

Table 3

TEA1069 and TEA1069A basic states

NAME

FREQUENCY (Hz)

DURATION (ms)

Bell 1

800 + 1066 + 1333

28 + 28 + 28

Bell 2

826 + 925 + 1027

28 + 28 + 28

Bell 3

1037 + 1161 + 1297 28 + 28 + 28

Bell 4

1297 + 1455 + 1621 28 + 28 + 28

INPUT CSI

INPUT CE/FDI

STATE

LOW

standby

HIGH

LOW

not applicable

LOW

HIGH

ringer

HIGH

on-line

For the hands-free state refer to Fig.23.

PULSE DIALLER: PINS DP/FL, MOH/DMO AND MUTE

The pulse dialling system uses line current interruptions to

signal the digits dialled to the exchange. The number of

line current interruptions corresponds with the digit dialled

except for the digit [0] which is characterized by

10 interruptions. Before each digit there is an inter-digit

pause.

Valid keys are the digits [0] to [9] and [PAUSE].

The pulse dialling mode, the make/break ratio and the

access pause time depend on the diode options: PTS,

M/B, APT and APT2. DP/FL is LOW when VDD is below

power-on reset trip level and when RESET is HIGH.

The MOH/DMO pin (diode GOS = on) is used to reduce

the voltage swing over the a/b terminals during pulse

dialling. Several countries require this feature. The MUTE

pin is an open drain output which requires a pull-up

resistor. MUTE is HIGH when VDD is below power-on reset

trip level and when RESET is HIGH.

Figure 13 shows the timing diagram in pulse dialling mode

when keys [3], [RECALL] and [4] are pressed.

TEA1069 Datasheet(PDF) 15 Page - NXP Semiconductors

TEA1069 Datasheet(HTML) 15 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL