COP8SCE9HMT7 datasheet(21/70 Pages) NSC

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4.0 Functional Description (Continued)

in mode 1, T1 Underflow in Mode 2, T1A capture

edge in mode 3)

T1ENA

Timer T1 Interrupt Enable for Timer Underflow

or T1A Input capture edge

EXPND

External interrupt pending

BUSY

MICROWIRE/PLUS busy shifting flag

EXEN

Enable external interrupt

GIE

Global interrupt enable (enables interrupts)

The Half-Carry flag is also affected by all the instructions that

affect the Carry flag. The SC (Set Carry) and R/C (Reset

Carry) instructions will respectively set or clear both the carry

flags. In addition to the SC and R/C instructions, ADC,

SUBC, RRC and RLC instructions affect the Carry and Half

Carry flags.

ICNTRL Register (Address X'00E8)

Unused

LPEN

T0PND

T0EN

µWPND

µWEN

T1PNDB

T1ENB

Bit 7

Bit 0

The ICNTRL register contains the following bits:

LPEN

Port

Interrupt

Enable

(Multi-Input

Wake-up/Interrupt)

T0PND

Timer T0 Interrupt pending

T0EN

Timer T0 Interrupt Enable (Bit 12 toggle)

µWPND MICROWIRE/PLUS interrupt pending

µWEN

Enable MICROWIRE/PLUS interrupt

T1PNDB Timer T1 Interrupt Pending Flag for T1B capture

edge

T1ENB

Timer T1 Interrupt Enable for T1B Input capture

edge

T2CNTRL Register (Address X'00C6)

T2C3

T2C2

T2C1

T2C0

T2PNDA

T2ENA

T2PNDB

T2ENB

Bit 7

Bit 0

The T2CNTRL register contains the following bits:

T2C3

Timer T2 mode control bit

T2C2

Timer T2 mode control bit

T2C1

Timer T2 mode control bit

T2C0

Timer

Start/Stop

control

timer

modes 1 and 2, Timer T2 Underflow Interrupt

Pending Flag in timer mode 3

T2PNDA Timer T2 Interrupt Pending Flag (Autoreload

RA in mode 1, T2 Underflow in mode 2, T2A

capture edge in mode 3)

T2ENA

Timer T2 Interrupt Enable for Timer Underflow

or T2A Input capture edge

T2PNDB Timer T2 Interrupt Pending Flag for T2B cap-

ture edge

T2ENB

Timer T2 Interrupt Enable for T2B Input capture

edge

HSTCR Register (Address X'00AF)

Reserved

T2HS

Bit 7

Bit 0

The HSTCR register contains the following bits:

T2HS Places Timer T2 in High Speed Mode.

ITMR Register (Address X'00CF)

LSON

HSON

DCEN

CCKS

RSVD

ITSEL2

ITSEL1

ITSEL0

Bit 7

Bit 0

The ITMR register contains the following bits:

LSON

Turns the low speed oscillator on or off.

HSON

Turns the high speed oscillator on or off.

DCEN

Selects the high speed oscillator or the low

speed oscillator as the Idle Timer Clock.

CCKSEL Selects the high speed oscillator or the low

speed oscillator as the primary CPU clock.

RSVD

This bit is reserved and must be 0.

ITSEL2

Idle Timer period select bit.

ITSEL1

Idle Timer period select bit.

ITSEL0

Idle Timer period select bit.

5.0 In-System Programming

5.1 INTRODUCTION

This device provides the capability to program the program

memory while installed in an application board. This feature

is called In System Programming (ISP). It provides a means

of ISP by using the MICROWIRE/PLUS, or the user can

provide his own, customized ISP routine. The factory in-

stalled ISP uses the MICROWIRE/PLUS port. The user can

provide his own ISP routine that uses any of the capabilities

of the device, such as USART, parallel port, etc.

5.2 FUNCTIONAL DESCRIPTION

The organization of the ISP feature consists of the user flash

program memory, the factory boot ROM, and some registers

dedicated to performing the ISP function. See

Figure 13 for

a simplified block diagram. The factory installed ISP that

uses MICROWIRE/PLUS is located in the Boot ROM. The

size of the Boot ROM is 1k bytes and also contains code to

facilitate in system emulation capability. If a user chooses to

write his own ISP routine, it must be located in the flash

program memory.

As described in

4.5 OPTION REGISTER, there is a bit,

FLEX, that controls whether the device exits RESET execut-

ing from the flash memory or the Boot ROM. The user must

program the FLEX bit as appropriate for the application. In

the erased state, the FLEX bit = 0 and the device will

20032717

FIGURE 13. Block Diagram of ISP

COP8SCE9HMT7 Datasheet(PDF) 21 Page - National Semiconductor (TI)

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