COP8SCE9HMT7 datasheet(13/70 Pages) NSC

13 / 70 page

3.0 Pin Descriptions

The COP8SBE/SCE/SDE I/O structure enables designers to

reconfigure the microcontroller’s I/O functions with a single

instruction. Each individual I/O pin can be independently

configured as output pin low, output high, input with high

impedance or input with weak pull-up device. A typical ex-

ample is the use of I/O pins as the keyboard matrix input

lines. The input lines can be programmed with internal weak

pull-ups so that the input lines read logic high when the keys

are all open. With a key closure, the corresponding input line

will read a logic zero since the weak pull-up can easily be

overdriven. When the key is released, the internal weak

pull-up will pull the input line back to logic high. This elimi-

nates the need for external pull-up resistors. The high cur-

rent options are available for driving LEDs, motors and

speakers. This flexibility helps to ensure a cleaner design,

with less external components and lower costs. Below is the

general description of all available pins.

CC and GND are the power supply pins. All VCC and GND

pins must be connected.

Users of the LLP package are cautioned to be aware that the

central metal area and the pin 1 index mark on the bottom of

the package may be connected to GND. See figure below:

CKI is the clock input. This can be connected (in conjunction

with CKO) to an external crystal circuit to form a crystal

oscillator. See Oscillator Description section.

RESET is the master reset input. See Reset description

section.

The device contains up to six bidirectional 8-bit I/O ports (A,

B, G, H and L), where each individual bit may be indepen-

dently configured as an input (Schmitt trigger inputs on ports

L and G), output or TRI-STATE under program control. Three

data memory address locations are allocated for each of

these I/O ports. Each I/O port has three associated 8-bit

memory mapped registers, the CONFIGURATION register,

the output DATA register and the Pin input register. (See the

memory map for the various addresses associated with the

I/O ports.)

Figure 3 shows the I/O port configurations. The

DATA and CONFIGURATION registers allow for each port bit

to be individually configured under software control as

shown below:

CONFIGURATION

DATA

Port Set-Up

Hi-Z Input

(TRI-STATE Output)

CONFIGURATION

DATA

Port Set-Up

Input with Weak Pull-Up

Push-Pull Zero Output

Push-Pull One Output

Port A is an 8-bit I/O port. All A pins have Schmitt triggers on

the inputs. The 44-pin packages do not have a full 8-bit port

and contain some unbonded, floating pads internally on the

chip. The binary value read from these bits is undetermined.

The application software should mask out these unknown

bits when reading the Port A register, or use only bit-access

program instructions when accessing Port A. These uncon-

nected bits draw power only when they are addressed (i.e.,

in brief spikes).

Port B is an 8-bit I/O port. All B pins have Schmitt triggers on

the inputs.

Port G is an 8-bit port. Pin G0, G2–G5 are bi-directional I/O

ports. Pin G6 is always a general purpose Hi-Z input. All pins

have Schmitt Triggers on their inputs. Pin G1 serves as the

dedicated WATCHDOG output with weak pull-up if the

WATCHDOG feature is selected by the Option register.

The pin is a general purpose I/O if WATCHDOG feature is

not selected. If WATCHDOG feature is selected, bit 1 of the

Port G configuration and data register does not have any

effect on Pin G1 setup. G7 serves as the dedicated output

pin for the CKO clock output.

Since G6 is an input only pin and G7 is the dedicated CKO

clock output pin, the associated bits in the data and configu-

ration registers for G6 and G7 are used for special purpose

functions as outlined below. Reading the G6 and G7 data

bits will return zeros.

The device will be placed in the HALT mode by writing a “1”

to bit 7 of the Port G Data Register. Similarly the device will

be placed in the IDLE mode by writing a “1” to bit 6 of the

Port G Data Register.

Writing a “1” to bit 6 of the Port G Configuration Register

enables the MICROWIRE/PLUS to operate with the alter-

nate phase of the SK clock. The G7 configuration bit, if set

high, enables the clock start up delay after HALT when the

R/C clock configuration is used.

Config. Reg.

Data Reg.

CLKDLY

HALT

Alternate SK

IDLE

Port G has the following alternate features:

G7 CKO Oscillator dedicated output

G6 SI (MICROWIRE/PLUS Serial Data Input)

G5 SK (MICROWIRE/PLUS Serial Clock)

G4 SO (MICROWIRE/PLUS Serial Data Output)

G3 T1A (Timer T1 I/O)

G2 T1B (Timer T1 Capture Input)

G1 WDOUT WATCHDOG and/or Clock Monitor if WATCH-

DOG enabled, otherwise it is a general purpose I/O

G0 INTR (External Interrupt Input)

G0 through G3 are also used for In-System Emulation.

Port H is an 8-bit I/O port. All H pins have Schmitt triggers on

the inputs.

Port L is an 8-bit I/O port. All L-pins have Schmitt triggers on

the inputs.

Port L supports the Multi-Input Wake-up feature on all eight

pins. Port L has the following alternate pin functions:

20032770

FIGURE 2.

COP8SCE9HMT7 Datasheet(PDF) 13 Page - National Semiconductor (TI)

COP8SCE9HMT7 Datasheet(HTML) 13 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

Datasheet Download

Link URL