Philips Semiconductors

Product specification

TPM749

Microcontroller with TrackPoint

™ microcode from IBM

1996 May 01

5

OSCILLATOR CHARACTERISTICS

X1 and X2 are the input and output, respectively, of an inverting

amplifier which can be configured for use as an on-chip oscillator.

To drive the device from an external clock source, X1 should be

driven while X2 is left unconnected. There are no requirements on

the duty cycle of the external clock signal, because the input to the

internal clock circuitry is through a divide-by-two flip-flop. However,

minimum and maximum high and low times specified in the data

sheet must be observed.

IDLE MODE

The TPM includes the 80C51 power-down and idle mode features.

In idle mode, the CPU puts itself to sleep while all of the on-chip

peripherals except the A/D and PWM stay active. The functions that

continue to run while in the idle mode are Timer 0, Timer I, and the

interrupts. The instruction to invoke the idle mode is the last

instruction executed in the normal operating mode before the idle

mode is activated. The CPU contents, the on-chip RAM, and all of

the special function registers remain intact during this mode. The

idle mode can be terminated either by any enabled interrupt (at

which time the process is picked up at the interrupt service routine

and continued), or by a hardware reset which starts the processor in

the same manner as a power-on reset. Upon powering-up the

circuit, or exiting from idle mode, sufficient time must be allowed for

stabilization of the internal analog reference voltages before an A/D

conversion is started.

POWER-DOWN MODE

In the power-down mode, the oscillator is stopped and the

instruction to invoke power-down is the last instruction executed.

Only the contents of the on-chip RAM are preserved. A hardware

reset is the only way to terminate the power-down mode. The control

bits for the reduced power modes are in the special function register

PCON.

Table 1. External Pin Status During Idle and

Power-Down Modes

MODE

Port 0*

Port 1

Port 2

Idle

Data

Data

Data

Power-down

Data

Data

Data

*

Except for PWM output (P0.4).

I/O Ports

The I/O pins provided by the TPM consist of port 0, port 1, and

port 3.

Port 0

Port 0 is a 5-bit bidirectional I/O port and includes alternate functions

on some pins of this port. Pins P0.3 and P0.4 are provided with

internal pullups while the remaining pins (P0.0, P0.1, and P0.2) have

open drain output structures. The alternate function for port P0.4 is

PWM output.

If the alternate function PWM is not being used, then this pin may be

used as an I/O port.

Port 1

Port 1 is an 8-bit bidirectional I/O port whose structure is identical to

the 80C51, but also includes alternate input functions on all pins.

The alternate pin functions for port 1 are:

P1.0-P1.4 - ADC0-ADC4 - A/D converter analog inputs

P1.5 INT0 - external interrupt 0 input

P1.6 INT1 - external interrupt 1 input

P1.7 - T0 - timer 0 external input

If the alternate functions INT0, INT1, or T0 are not being used, these

pins may be used as standard I/O ports. It is necessary to connect

P1.6, and P1.7 pins as standard I/O pins. When the A/D converter is

enabled, the analog channel connected to the A/D may not be used

as a digital input; however, the remaining analog inputs may be used

as digital inputs. They may not be used as digital outputs. While the

A/D is enabled, the analog inputs are floating.

Port 3

Port 3 is an 8-bit bidirectional I/O port whose structure is identical to

the 80C51. Note that the alternate functions associated with port 3

of the 80C51 have been moved to port 1 of the TPM (as applicable).

See Figure 1 for port bit configurations.

P1.X

LATCH

D

Q

CL

Q

READ

LATCH

INT. BUS

WRITE TO

LATCH

READ

PIN

ALTERNATE INPUT

FUNCTION

VDD

P1.X

PIN

INTERNAL

PULL-UP

ALTERNATE

OUTPUT

FUNCTION

P0.X

LATCH

D

Q

CL

Q

READ

LATCH

INT. BUS

WRITE TO

LATCH

READ

PIN

ALTERNATE INPUT

FUNCTION

P0.X

PIN

ALTERNATE

OUTPUT

FUNCTION

SU00306

Figure 1. Port Bit Latches and I/O Buffers