TSA5059ATS datasheet(8/24 Pages) PHILIPS

8 / 24 page

2000 Oct 24

Philips Semiconductors

Product speciﬁcation

2.7 GHz I2C-bus controlled low phase

noise frequency synthesizer

TSA5059A

READ mode: R/W=1

Data can be read out of the TSA5059A by setting bit R/W

to logic 1 (see Table 5). After the slave address has been

recognized, the TSA5059A generates an acknowledge

and the first data byte (status word) is transferred on the

SDA line. Data is valid on the SDA line during a

HIGH-level of the SCL clock signal.

A second data byte can be read out of the TSA5059A if the

controller generates an acknowledge on the SDA line.

End of transmission will occur if no acknowledge from the

controller occurs. The TSA5059A will then release the

data line to allow the controller to generate a STOP

condition. When ports P0 to P2 are used as inputs, they

must be programmed in their high-impedance state.

The POR flag is set to logic 1 when VCC drops below

approximately 2.75 V and at power-on.

It is reset to logic 0 when an end of data is detected by the

TSA5059A (end of a READ sequence).

Control of the loop is made possible with the in-lock flag

which indicates when the loop is phase-locked (bit FL = 1).

The bits I2, I1 and I0 represent the status of the I/O ports

P2, P1 and P0 respectively. A logic 0 indicates a

LOW-level and a logic 1 indicates a HIGH-level.

A built-in 5-level ADC is available at pin ADC. This

converter can be used to feed AFC information to the

microcontroller through the I2C-bus. The relationship

between bits A2, A1, A0 and the input voltage at pin ADC

is given in Table 7.

Table 5

Read data format

Note

1. MSB is transmitted first.

Table 6

Explanation of Table 5

Table 7

ADC levels

Note

1. Accuracy is

±0.03VCC.

BYTE

DESCRIPTION

MSB(1)

LSB

CONTROL BIT

address

MA1

MA0

status byte

POR

−

BIT

DESCRIPTION

acknowledge bit

MA1 and MA0

programmable address bits; see Table 3

POR

Power-on reset ﬂag (bit POR = 1 at power-on)

in-lock ﬂag (bit FL = 1 when the loop is phase-locked)

I2, I1 and I0

digital information for I/O ports P2, P1 and P0 respectively

A2, A1 and A0

digital outputs of the 5-level ADC; see Table 7

VOLTAGE APPLIED TO PIN ADC(1)

0.6VCC to VCC

0.45VCC to 0.6VCC

0.3VCC to 0.45VCC

0.15VCC to 0.3VCC

0 to 0.15VCC

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