12F615 datasheet(99/168 Pages) MICROCHIP

99 / 168 page

Preliminary

DS41302A-page 97

PIC12F609/615/12HV609/615

11.3.4

BROWN-OUT RESET (BOR)

The BOREN0 and BOREN1 bits in the Configuration

Word register select one of three BOR modes. One

mode has been added to allow control of the BOR

enable for lower current during Sleep. By selecting

BOREN<1:0> = 10, the BOR is automatically disabled

in Sleep to conserve power and enabled on wake-up.

See

for

the

Configuration

Word

definition.

A brown-out occurs when VDD falls below VBOR for

greater than parameter TBOR (see Section 15.0

“Electrical Specifications”). The brown-out condition

will reset the device. This will occur regardless of VDD

slew rate. A Brown-out Reset may not occur if VDD falls

below VBOR for less than parameter TBOR.

On any Reset (Power-on, Brown-out Reset, Watchdog

timer, etc.), the chip will remain in Reset until VDD rises

above VBOR (see Figure 11-3). If enabled, the Power-

up Timer will be invoked by the Reset and keep the chip

in Reset an additional 64 ms.

If VDD drops below VBOR while the Power-up Timer is

running, the chip will go back into a Brown-out Reset

and the Power-up Timer will be re-initialized. Once VDD

rises above VBOR, the Power-up Timer will execute a

64 ms Reset.

11.3.5

BOR CALIBRATION

The PIC12F609/615/12HV609/615 stores the BOR

calibration values in fuses located in the Calibration

Word register (2008h). The Calibration Word register is

not erased when using the specified bulk erase

sequence in the “PIC12F6XX/16F6XX Memory Pro-

gramming Specification” (DS41204) and thus, does not

require reprogramming.

FIGURE 11-3:

BROWN-OUT SITUATIONS

Note:

The Power-up Timer is enabled by the

PWRTE bit in the Configuration Word

Note:

Address 2008h is beyond the user pro-

gram memory space. It belongs to the

special

configuration

memory

space

(2000h-3FFFh), which can be accessed

only

during

programming.

See

“PIC12F6XX/16F6XX Memory Program-

ming Specification” (DS41204) for more

information.

64 ms(1)

VBOR

VDD

Internal

Reset

VBOR

VDD

Internal

Reset

64 ms(1)

< 64 ms

64 ms(1)

VBOR

VDD

Internal

Reset

Note 1:

64 ms delay only if PWRTE bit is programmed to ‘0’.

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