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12F615 Datasheet(PDF) 148 Page - Microchip Technology |
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12F615 Datasheet(HTML) 148 Page - Microchip Technology |
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148 / 168 page ![]() PIC12F609/615/12HV609/615 DS41302A-page 146 Preliminary © 2006 Microchip Technology Inc. TABLE 15-12: PIC12F615/HV615 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristic Min Typ† Max Units Conditions AD130* TAD A/D Clock Period 1.6 — 9.0 μsTOSC-based, VREF ≥ 3.0V 3.0 — 9.0 μsTOSC-based, VREF full range(3) A/D Internal RC Oscillator Period 3.0 6.0 9.0 μs ADCS<1:0> = 11 (ADRC mode) At VDD = 2.5V 1.6 4.0 6.0 μsAt VDD = 5.0V AD131 TCNV Conversion Time (not including Acquisition Time)(1) —11 — TAD Set GO/DONE bit to new data in A/D Result register AD132* TACQ Acquisition Time 11.5 — μs AD133* TAMP Amplifier Settling Time — — 5 μs AD134 TGO Q4 to A/D Clock Start — — TOSC/2 TOSC/2 + TCY — — — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle. 2: See Section 9.3 “A/D Acquisition Requirements” for minimum conditions. 3: Full range for PIC12HV609/HV615 powered by the shunt regulator is the 5V regulated voltage. |
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