TPS65131 datasheet(21/44 Pages) TI

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8.4 Layout

8.4.1 Layout Guidelines

As for all switching power supplies, the layout is an important step in the design, especially at high peak currents

and high switching frequencies. Improper layout might show the symptoms of poor line or load regulation,

ground and output voltage shifts, stability issues, unsatisfying EMI behavior or worsened efficiency. Therefore,

use wide and short traces for the main current paths and for the power ground tracks. The input capacitors

(C1, C2, C3), output capacitors (C4, C5), the inductors (L1, L2), and the rectifying diodes (D1, D2) should be

placed as close as possible to the IC to keep parasitic inductances low. Use a wide PGND plane. Connect the

analog ground pin (AGND) to the PGND plane. Further, connect the PGND plane with the exposed thermal pad.

Place the feedback dividers as close as possible to the control pin (boost converter) or the VREF pin (inverting

converter) of the IC.

Figure 8-21 provides an layout example which is recommended to be followed.

8.4.2 Layout Example

VNEG

VPOS

PGND

PSN

ENN

PSP

ENP

BSW

AGND

FBP

VPOS

INP

C10

Figure 8-21. TPS65131-Q1 Layout Recommendation

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TPS65131-Q1

SLVSBB2F – MAY 2012 – REVISED AUGUST 2024

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TPS65131 Datasheet(PDF) 21 Page - Texas Instruments