TPSM83102 datasheet(13/31 Pages) TI

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Table 7-3. Register CONTROL1 Field Descriptions

Bit

Field

Type

Reset

Description

7:4

NIL

0b0000

Not used.

During write operations data for these bits are ignored. During read operations 0 is

returned

EN_FAST_DVS

R/W

0b1

Sets DVS to fast mode

0 : DISABLE, 1 : ENABLE

EN_SCP

R/W

0b0

Enable short circuit hiccup protection

0 : DISABLE, 1 : ENABLE

NIL

0b0

Not used.

CONVERTER_EN R/W

0b0

Enable Converter ('AND'ed with EN-pin)

0 : DISABLE, 1 : ENABLE

7.6.1.3 Register VOUT (Register address: 0x03; Default: 0x5C)

Return to Register Map

Table 7-4. Register VOUT Format

VOUT[7 :0]

R/W

LEGEND: R/W = Read/Write

Table 7-5. Register VOUT Field Descriptions

Bit

Field

Type

Reset

Description

7:0

VOUT[7:0]

R/W

0x5C

These bits set the output voltage

Output voltage = 1.000 + (VOUT[7 :0] × 0.025) V when 0x00<=VOUT[7 :0]<=0xB4;

Output voltage = 5.5 V when 0xB5<=VOUT[7 :0]<=0xFF

7.6.1.4 Register CONTROL2 (Register address: 0x05; Default: 0x45)

Return to Register Map

Table 7-6. Register CONTROL2 Format

FPWM

FAST_RAMP_E

EN_DISCH_VOUT[1:0]

CL_RAMP_MIN

TD_RAMP[2:0]

R/W

LEGEND: R/W = Read/Write

Table 7-7. Register CONTROL2 Field Descriptions

Bit

Field

Type

Reset

Description

FPWM

R/W

0b0

Force PWM operation

0 : DISABLE, 1 : ENABLE

FAST_RAMP_EN

R/W

0b1

Device can start-up faster then VOUT ramp

0 : DISABLE, 1 : ENABLE

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TPSM83102, TPSM83103

SLVSH13 – AUGUST 2024

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