REV. 0

AD7843

–14–

Sixteen Clocks per Cycle

The control bits for the next conversion can be overlapped with

the current conversion to allow for a conversion every 16 DCLK

cycles, as shown in Figure 11. This timing diagram also allows

for the possibility of communication with other serial peripherals

between each (eight DCLK) byte transfer between the processor

and the converter. However, the conversion must be complete

within a short enough time frame to avoid capacitive droop

effects which may distort the conversion result. It should also

be noted that the AD7843 will be fully powered while other

serial communications may be taking place between byte transfers.

Fifteen Clocks per Cycle

Figure 12 shows the fastest way to clock the AD7843. This

scheme will not work with most microcontrollers or DSPs as in

general they are not capable of generating a 15-clock cycle per

serial transfer. However, some DSPs will allow the number of

clocks per cycle to be programmed and this method could also

be used with FPGAs (Field Programmable Gate Arrays) or

ASICs (Application Specific Integrated Circuits). As in the 16-

clocks-per-cycle case, the control bits for the next conversion

are overlapped with the current conversion to allow for a con-

version every 15 DCLK cycles, using 12 DCLKs to perform

the conversion and three DCLKs to acquire the analog input.

This will effectively increase the throughput rate of the AD7843

beyond that used for the specifications which are tested using 16

DCLKs per cycle, and DCLK = 2 MHz.

8-Bit Conversion

The AD7843 can be set up to operate in an 8-bit rather than

12-bit mode, by setting the MODE bit to 1 in the control regis-

ter. This mode allows a faster throughput rate to be achieved,

assuming 8-bit resolution is sufficient. When using the 8-bit

mode a conversion is complete four clock cycles earlier than in

the 12-bit mode. This could be used with serial interfaces that

provide 12 clock transfers, or two conversions could be com-

pleted with three eight-clock transfers. The throughput rate will

increase by 25% as a result of the shorter conversion cycle, but

the conversion itself can occur at a faster clock rate because the

internal settling time of the AD7843 is not as critical because

settling to 8 bits is all that is required. The clock rate can be as

much as 50% faster. The faster clock rate and fewer clock cycles

combine to provide double the conversion rate.

PEN INTERRUPT REQUEST

The pen interrupt equivalent output circuitry is outlined in

Figure 13. By connecting a pull-up resistor (10 k

Ω to 100 kΩ)

PENIRQ output will remain high normally. If PENIRQ has

CS

DCLK

1

8

DOUT

DIN

8

1

8

1

S

BUSY

10

9

8

11

76

5

4

3

2

10

CONTROL BITS

S

CONTROL BITS

10

9

11

1

Figure 11. Conversion Timing, 16 DCLKS per Cycle, 8-Bit Bus Interface. No DCLK Delay Required with Dedicated Serial Port

DCLK

1

15

1

10

9

8

11

7

6

5

4

3

2

10

S

10

9

1

DOUT

DIN

15

S

BUSY

8

7

S

A2

A2

A1

A0

PD1 PD0

A1

A0

SER/

DFR

PD1 PD0

A2

654

MODE

SER/

DFR

11

MODE

CS

Figure 12. Conversion Timing, 15 DCLKS per Cycle, Maximum Throughput Rate