MAX26402/MAX26403

36V, 2.5A/3.5A, Fully Integrated Synchronous

Silent Switcher Buck Converters

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Analog Devices | 13

• Place the input capacitors in a symmetrical configuration, with a 2.2µF (min) input capacitor on each SUP pin, close

to the device. For additional noise immunity, when adding a high-frequency ceramic input-bypass capacitor (CBP) on

each SUP pin, first place the high-frequency capacitor as close to the pin as possible, followed by the 2.2µF capacitor.

Place the ceramic capacitors as close as possible to the SUP and PGND pins on both sides of the IC. Use low-

impedance connections (no vias or other discontinuities) between the capacitors and IC pins. The CBP should be

located closest to the IC and should have very good high-frequency performance (small package size and high

capacitance). This provides the best EMI rejection and minimize internal noise on the device, which can degrade

performance.

• Connect PGND and GND pins directly under the IC. This ensures the shortest connection path between GND and

PGND.

• Place the BIAS capacitor as close to the IC BIAS pin as possible to reduce the bias current loop. This helps to reduce

noise on BIAS for smooth operation.

• Place the bootstrap capacitor CBST close to the IC and use short, wide traces to minimize the loop area and to

minimize the parasitic inductance. Use the nearest layer for a return trace (CBST to LX) to minimize the inductance

further. Refer to the layout in the EV kit for optimum design. High parasitic inductance can impact switching speed

(increase switching losses) and cause high dV/dt noise.

• Place the inductor as close to the IC LX pin as possible and minimize the area of the LX node.

• Place the output capacitors in a symmetrical configuration on opposite sides of the inductor for best noise immunity.

Place the output capacitors (COUT) near the inductor so that the ground side of COUT is near the CIN ground connection

to minimize the current-loop area. Add vias on the capacitor ground to minimize the inductance. For additional noise

immunity, place a high-frequency capacitor on each side of the inductor, followed by the output capacitors to further

reduce the radiated noise.

• Place the inductor, output capacitors, bootstrap capacitor, and BIAS capacitor in such a way as to minimize the area

enclosed by the current loops. Keep the power traces and load connections short. This practice is essential for high

efficiency. Use a thick copper PCB to enhance full-load efficiency and power-dissipation capability.

• Use internal PCB layers as ground planes to help improve the EMI, as ground planes act as a shield against radiated

noise. Spread multiple vias around the board, especially near the ground connections.

• Use a continuous copper GND plane on the layer next to the IC to shield the entire circuit. The GND should also be

poured around the entire circuit on the top side. Ensure that all heat-dissipating components have adequate

connections to copper for cooling. Use multiple vias to interconnect GND planes/areas for low impedance and

maximum heat dissipation. Place vias at the GND terminals of the IC and input/output/bypass capacitors. Do not

separate or isolate PGND and GND connections with separate planes or areas.

• Place the feedback resistor-divider (if used) near the IC and route the feedback and OUT connections away from the

inductor and LX node and other noisy signals.