CS4360

DS517F2

23

4.3.2

Control Port Mode

The desired format is selected via the DIF2, DIF1 and DIF0 bits in the Mode Control 2 register (see section

6.1.2). For an illustration of the required relationship between LRCK, SCLK and SDIN, see Figures 15-17.

4.4

De-Emphasis Control

44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in

sample rate, Fs.

Notes: De-emphasis is only available in Single-speed Mode.

LR C K

SC L K

Left C hannel

R ig ht C hannel

SD IN

+3 +2 +1

+5 +4

MS B

-1 - 2 -3 -4 -5

+3 +2 +1

+5 +4

-1 -2 -3 -4

LS B

MS B

LS B

Figure 15. Left Justified up to 24-Bit Data

LR C K

SC L K

Left C hannel

R ig ht C hannel

SD IN

+3 +2 +1

+5 +4

MS B

-1 - 2 -3 -4 -5

+3 +2 +1

+5 +4

-1 -2 - 3 -4

MS B

LS B

LS B

LRCK

SC LK

Left C hannel

SDIN

+6 +5 +4 +3

+2 +1

+7

-1 -2 -3 -4 -5

LS B

Right Cha nnel

MSB

LS B

+6 +5 +4 +3 +2 +1

+7

-1 -2 -3 -4 -5

MSB

LSB

Figure 17. Right Justified Data

Gain

dB

-10dB

0dB

Frequency

T2 = 15 µs

T1=50 µs

F1

F2

3.183 kHz

10.61 kHz

Figure 18. De-emphasis Curve