12

DS684F2

CS4352

4.3

Digital Interface Format

The device will accept audio samples in 1 of 4 digital interface formats, as illustrated in Table 5.

The desired format is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship

between the LRCK, SCLK and SDIN, see Figures 3-5. For all formats, SDIN is valid on the rising edge of

SCLK. Also, SCLK must have at least 32 cycles per LRCK period in format 2 and 48 cycles per LRCK period

in format 3.

For more information about serial audio formats, refer to Cirrus Logic Application Note AN282: The 2-Chan-

Table 5. Digital Interface Format

Figure 3. I²S, up to 24-Bit Data

Figure 4. Right-Justified Data

Figure 5. Left-Justified up to 24-Bit Data

DIF1

DIF0

DESCRIPTION

FORMAT

FIGURE

00

I²S, up to 24-bit Data

0

3

01

Right-Justified, 24-bit Data

1

4

10

Left-Justified, up to 24-bit Data

2

5

11

Right-Justified, 16-bit Data

3

4

LR C K

SCL K

Le ft C h a n n e l

Rig h t Ch an n e l

SD IN

+3 +2 +1

+5 +4

MS B

-1 -2 -3 -4 -5

+3 +2 +1

+5 +4

-1 -2 -3 -4

MS B

LS B

LS B

L RCK

SC LK

Le ft C h a n n e l

SD IN

-6 -5 -4 -3 -2 -1

-7

+1 +2 +3 +4 +5

MS B

R ig h t C ha nn el

LS B

MS B

+1 +2 +3 +4 +5

LS B

-6 -5 -4 -3 -2 -1

-7

MS B

LR C K

SC L K

Left C ha nnel

R ig h t C ha n nel

SDIN

+3 +2 +1

+5 +4

MS B

-1 -2 -3 -4 -5

+3 +2 +1

+5 +4

-1 -2 -3 -4

LSB

MSB

LS B