1250A—07/31/07

Advance Information

ICS9DBL411

Four Output Differential Buffer for PCI Express

3

TSSOP Pin Description

PIN #

(TSSOP)

PIN NAME

PIN TYPE

DESCRIPTION

1OE0#

IN

Output Enable for DIF0 output. Control is as follows:

0 = enabled, 1 = Low-Low

2

DIF_INC

IN

Complement side of differential input clock

3

DIF_INT

IN

True side of differential input clock

4

VDDA

PWR

3.3V Power for the Analog Core

5

GNDA

GND

Ground for the Analog Core

6OE3#

IN

Output Enable for DIF3 output. Control is as follows:

0 = enabled, 1 = Low-Low

7

DIF3C_LPR

OUT

Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)

8

DIF3T_LPR

OUT

True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)

9

VDD_IO

PWR

Power supply for low power differential outputs, nominal 1.05V to 3.3V

10

GND

GND

Ground pin

11

DIF2C_LPR

OUT

Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)

12

DIF2T_LPR

OUT

True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)

13

OE2#

IN

Output Enable for DIF2 output. Control is as follows:

0 = enabled, 1 = Low-Low

14

DIF1C_LPR

OUT

Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)

15

DIF1T_LPR

OUT

True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)

16

OE1#

IN

Output Enable for DIF1 output. Control is as follows:

0 = enabled, 1 = Low-Low

17

GND

GND

Ground pin

18

VDD_IO

PWR

Power supply for low power differential outputs, nominal 1.05V to 3.3V

19

DIF0C_LPR

OUT

Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)

20

DIF0T_LPR

OUT

True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)