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CS8416-CSZ Datasheet(PDF) 40 Page - Cirrus Logic

Part # CS8416-CSZ
Description  192 kHZ DIGITAL AUDIO INTERFACE RECEIVER
PDF  60 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS8416-CSZ Datasheet(HTML) 40 Page - Cirrus Logic

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DS578F3
CS8416
TX_SEL[2:0]
– Selects RXP0 to RXP7 as the input for GPO TX source
Default =’001’
000 – RXP0
001 – RXP1, etc
14.7 Serial Audio Data Format (05h)
SOMS
- Master/Slave Mode Selector
Default = ‘0’
0 - Serial audio output port is in slave mode. OSCLK and OLRCK are inputs.
1 - Serial audio output port is in master mode. OSCLK and OLRCK are outputs.
SOSF
- OSCLK frequency (for master mode)
Default = ‘0’
0 - OSCLK output frequency is 64*Fs.
1 - OSCLK output frequency is 128*Fs.
SORES[1:0]
- Resolution of the output data on SDOUT
Default = ‘00’
00 - 24-bit resolution.
01 - 20-bit resolution.
10 - 16-bit resolution.
11 - Direct copy of the received NRZ data from the AES3 receiver including C, U, and V bits. The time slot
occupied by the Z bit is used to indicate the location of the block start. This setting forces the SOJUST bit
to be “0”. When using this setting, the de-emphasis filter must be off.
SOJUST
- Justification of SDOUT data relative to OLRCK
Default = ‘0’
0 - Left-Justified.
1 - Right-Justified (master mode only and SORES
11).
SODEL
- Delay of SDOUT data relative to OLRCK, for Left-Justified data formats
(This control is only valid in Left-Justified Mode)
Default = ‘0’
0 - MSB of SDOUT data occurs in the first OSCLK period after the OLRCK edge.
1 - MSB of SDOUT data occurs in the second OSCLK period after the OLRCK edge.
SOSPOL
- OSCLK clock polarity
Default = ‘0’
0 - SDOUT is sampled on rising edges of OSCLK.
1 - SDOUT is sampled on falling edges of OSCLK.
76543210
SOMS
SOSF
SORES1
SORES0
SOJUST
SODEL
SOSPOL
SOLRPOL



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