MPC940LAC datasheet(6/11 Pages) IDT

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MPC940L

LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP

IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP

MPC940L REV 7 JUNE 5, 2007

Figure 1. LVCMOS_CLK MPC940L AC Test Reference for VCC = 3.3 V and VCC = 2.5 V

Figure 2. PECL_CLK MPC940L AC Test Reference for VCC = 3.3 V and VCC = 2.5 V

Figure 3. Propagation Delay (tPD) Test Reference

Figure 4. LVCMOS Propagation Delay (tPD)

Test Reference

Figure 5. Output Duty Cycle (DC)

Figure 6. Output-to-Output Skew TSK(O)

Figure 7. Output Transition Time Test Reference

Figure 8. Input Transition Time Test Reference

Pulse

Generator

Z = 50

Ω

RT = 50Ω

ZO = 50Ω

RT = 50Ω

ZO = 50Ω

MPC940L DUT

VTT

Differential Pulse

Generator

Z = 50

Ω

RT = 50Ω

ZO = 50Ω

RT = 50Ω

ZO = 50Ω

MPC940L DUT

VTT

VCC

VCC÷2

GND

VPP

VCMR

PCLK_CLK

tPD

LVCMOS_CLK

VCC

VCC ÷ 2

GND

tPD

VCC

VCC ÷ 2

GND

The time from the PLL controlled edge to the non controlled

edge, divided by the time between PLL controlled edges,

expressed as a percentage.

DC = tP/T0 x 100%

VCC

VCC ÷ 2

GND

The pin-to-pin skew is defined as the worst case difference

in propagation delay between any two similar delay paths

within a single device.

tSK(O)

VCC ÷ 2

GND

VOH

VCC ÷ 2

GND

VCC

VCC = 3.3 V VCC = 2.5 V

2.4

0.55

1.8 V

0.6 V

VCC = 3.3 V VCC = 2.5 V

2.0

0.8

1.7 V

0.7 V

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