STAC9271 datasheet(24/223 Pages) IDT

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STAC9271/9272/9273/9274

10-CHANNEL HIGH DEFINITION AUDIO CODEC

PC AUDIO

IDT™

10-CHANNEL HIGH DEFINITION AUDIO CODEC

STAC9271/9272/9273/9274 V 1.0 MARCH2007

IDT CONFIDENTIAL

Table 3. Valid Digital Microphone Configurations

Digital Mics

Date Sample

ADC Conn.

Notes

N/A

No Digital Microphones

Single Edge

0, 1, or 2

Available on either DMIC_0 or DMIC_1

Both ADC Channels produce data, may be in phase or out by

1/2 DMIC_CLK period depending upon external configuration

and timing

Double Edge

on either

DMIC_0 or 1

Single Edge on

DMIC_0 and 1

0, 1, or 2

Available on either DMIC_0 or DMIC_1, External logic

required to support sampling on a single Digital Mic pin

channel on rising edge and second Digital Mic right channel

on falling edge of DMIC_CLK for those digital microphones

that don’t support alternative clock edge capability. If both

DMIC_0 and DMIC_1 are used to support 2 digital

microphones, 2 separate ADC units will be used, however,

this configuration is not recommended since it consumes two

stereo ADC resources.

Double Edge

on one DMIC

pin and Single

Edge on the

second DMIC

pin.

0, 1, or 2

Requires both DMIC_0 or DMIC_1, External logic required to

support sampling on a single Digital Mic pin channel on rising

edge and second Digital Mic right channel on falling edge of

DMIC_CLK for those digital microphones that don’t support

alternative clock edge capability. Two ADC units are required

to support this configuration

Double Edge

0, 1, or 2

Connected to DMIC_0 and DMIC_1, External logic required

to support sampling on a single Digital Mic pin channel on

rising edge and second Digital Mic right channel on falling

edge of DMIC_CLK for those digital microphones that don’t

support alternative clock edge capability. Two ADC units are

required to support this configuration

Table 4. DMIC_CLK and DMIC_0,1 Operation During Power States

Power State

DMIC Widget

Enabled?

DMIC_CLK

Output

DMIC_0,1

Notes

Yes

Clock Capable Input Capable

DMIC_CLK Output is Enabled when either

DMIC_0 or DMIC_1 Input Widget is Enabled.

Otherwise, the DMIC_CLK remains Low

Yes

Clock Capable Input Capable

DMIC_CLK Output is Enabled when either

DMIC_0 or DMIC_1 Input Widget is Enabled.

Otherwise, the DMIC_CLK remains Low

Yes

Clock Disabled Input Disabled DMIC_CLK Remains Low

Yes

Clock Disabled Input Disabled DMIC_CLK Remains Low

D0-D3

Clock Disabled Input Disabled DMIC_CLK is HIGH-Z with Weak Pull-down

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