V103A

V103A Datasheet

1

11/18/05

Revision 3.2

Integrated Circuit Systems • 525 Race St reet, S an Jose, CA 95126 • tel (408) 297-1201 • ww w. icst. com

General Description

The V103A LVDS display interface transmitter is

primarily designed to support pixel data transmission

between a video processing engine and a digital video

display. The data rate supports up to SXGA+

resolutions and can be used in Plasma, Rear Projector,

Front Projector, CRT and LCD display applications. It

can also be used in other high-bandwidth parallel data

applications and provides a low EMI interconnect over

a low cost, low bus width cable up to several meters in

length.

The V103A converts 35 bits of CMOS/TTL data,

clocked on the rising or falling edge of an input clock

(selectable), into six LVDS (Low Voltage Differential

Signaling) serial data stream pairs. In video

applications the 35 bits is normally divided into 10 bits

for each R, G and B channel and 5 control bits.

When combined with the V104 LVDS display interface

receiver, the V103A + V104 combination provides a

35-bit wide, 90 MHz transport. The rate of each LVDS

channel is 630 Mbps for a 90MHz data input clock, 945

Mbps for 135MHz.

Features

temperature

including VGA, SVGA, XGA, SXGA, SXGA+, NTSC,

PAL, SDTV, and HDTV up to 1080I or 720P

alignment

(selectable) to minimize EMI

reduced input voltage swing

Block Diagram

TA+

Parallel

to Serial

TA0-6

TA-

TB+

TB-

TC+

TC-

TD+

TD-

TE+

TE-

PLL

TB0-6

TC0-6

TE0-6

CLKIN

(8 to 135 MHz)

/PWDN

TD0-6

RS

R/F

7

7

7

7

7

TCLK+

TCLK-