PIMXRT804VCVL4A datasheet(114/119 Pages) NXP

114 / 119 page

i.MX RT1060 Crossover Processors for Consumer Products, Rev. 4, 04/2024

114

NXP Semiconductors

Revision history

Table 88 provides a revision history for this data sheet.

Table 88. i.MX RT1060 Data Sheet document revision history

Rev.

Number

Date

Substantive Change(s)

Rev.4

04/2024 • In Figure 2, "i.MX RT1060 system block diagram" :

– Added FlexIO1 and FlexIO2

– Updated FlexPWM (8-Channel x4) to (4-Channel x4).

– Updated Internal memory 96KB ROM to 128KB ROM, updated “GP Timer” instance to 2 and

removed ”Shared with TCM”

• Updated Figure 1, "Part number nomenclature—i.MX RT10XX family"

• Interchanged the Min. and Max. values of spec “System frequency/Bus frequency” in Table 10,

Operating ranges

• Added FlexIO3 in Table 2, i.MX RT1060 modules list.

• Added note in Table 3, Special signal considerations

• Added new part numbers “MIMXRT106VDVL6B”, “MIMXRT106CDVL6B”, “MIMXRT106DDVL6B”,

“MIMXRT106PDVL6B” and their relevant information in Table 1, Ordering information

• In Table 83, 10 x 10 mm functional contact assignments and Table 86, 12 x 12 mm functional contact

assignments for “GPIO_AD_B0_10”, updated the default status to output.

• In Section 4.2.1.1, Power-up sequence removed “VDDA_ADC_3P3” instance from note

”USB_OTG1_VBUS and USB_OTG2_VBUS are not part of the power....”

Rev. 3

03/2022 • Updated the Figure 1, "Part number nomenclature—i.MX RT10XX family"

• Updated the part number for MIMXRT106LDVL6A and MIMXRT106LDVL6B in the Table 1, Ordering

information

• Updated the Section 4.2.1.1, Power-up sequence

• Updated for FlexSPI x2 in the Section 3, Modules List

• Updated the Figure 19, "FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] =

0X0, 0X1"

• Updated row 6 in the Table 57, LPSPI Master mode timing

• Updated the Table 55, 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSAD)

• Updated the Figure 2, "i.MX RT1060 system block diagram"

Rev. 2

03/2021 • Added a new part number in the Table 1, Ordering information

• Updated the Figure 1, "Part number nomenclature—i.MX RT10XX family"

• Updated the baud rate of LPUART in the Table 2, i.MX RT1060 modules list

• Updated the descriptions of TEST_MODE in the Table 3, Special signal considerations

• Added system frequencies and bus frequencies in Table 10, Operating ranges; update the maximum

value of 3.3 V NVCC_EMC in the Table 10, Operating ranges

• Updated the maximum values of low-level output currents in the Table 22, Single voltage GPIO DC

parameters

• Added Default setting on reset columns and a footnote in the Table 83, 10 x 10 mm functional contact

assignments and Table 86, 12 x 12 mm functional contact assignments

Rev. 1

07/2020 • Changed the MPCore to core in the Section 1.1, Features

• Added new part numbers in the Table 1, Ordering information

• Updated the Figure 1, "Part number nomenclature—i.MX RT10XX family"

• Updated the frequency of RTC OSC in the Table 2, i.MX RT1060 modules list

• Updated conditions and maximum current of DCDC_IN in the Table 12, Maximum supply currents

• Added a restrictions in the Section 4.2.1.1, Power-up sequence

• Added IOH and IOL in the Table 22, Single voltage GPIO DC parameters

• Updated the minimum and maximum values in the Table 33, SEMC output timing in SYNC mode

PIMXRT804VCVL4A Datasheet(PDF) 114 Page - NXP Semiconductors

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