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PIMXRT802VCJM4A Datasheet(PDF) 19 Page - NXP Semiconductors

Part # PIMXRT802VCJM4A
Description  i.MX RT1060 Crossover Processors for Consumer Products
PDF  119 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PIMXRT802VCJM4A Datasheet(HTML) 19 Page - NXP Semiconductors

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Modules List
i.MX RT1060 Crossover Processors for Consumer Products, Rev. 4, 04/2024
NXP Semiconductors
19
uSDHC1
uSDHC2
SD/MMC and SDXC
Enhanced Multi-Media
Card / Secure Digital Host
Controller
Connectivity
Peripherals
i.MX RT1060 specific SoC characteristics:
All four MMC/SD/SDIO controller IPs are identical and
are based on the uSDHC IP. They are:
• Fully compliant with MMC command/response sets
and Physical Layer as defined in the Multimedia
Card System Specification, v4.5/4.2/4.3/4.4/4.41/
including high-capacity (size > 2 GB) cards HC
MMC.
• Fully compliant with SD command/response sets
and Physical Layer as defined in the SD Memory
Card Specifications, v3.0 including high-capacity
SDXC cards up to 2 TB.
• Fully compliant with SDIO command/response sets
and interrupt/read-wait mode as defined in the SDIO
Card Specification, Part E1, v3.0
Two ports support:
• 1-bit or 4-bit transfer mode specifications for SD and
SDIO cards up to UHS-I SDR104 mode (104 MB/s
max)
• 1-bit, 4-bit, or 8-bit transfer mode specifications for
MMC cards up to 52 MHz in both SDR and DDR
modes (104 MB/s max)
• 4-bit or 8-bit transfer mode specifications for eMMC
chips up to 200 MHz in HS200 mode (200 MB/s max)
WDOG1
WDOG2
Watch Dog
Timer Peripherals The watchdog (WDOG) Timer supports two comparison
points during each counting period. Each of the
comparison points is configurable to evoke an interrupt
to the Arm core, and a second point evokes an external
event on the WDOG line.
XBAR
Cross BAR
Cross Trigger
Each crossbar switch is an array of muxes with shared
inputs. Each mux output provides one output of the
crossbar. The number of inputs and the number of
muxes/outputs are user configurable and registers are
provided to select which of the shared inputs are routed
to each output.
Table 2. i.MX RT1060 modules list (continued)
Block Mnemonic
Block Name
Subsystem
Brief Description



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