PIMXRT201VCFP4A datasheet(54/119 Pages) NXP

54 / 119 page

i.MX RT1060 Crossover Processors for Consumer Products, Rev. 4, 04/2024

NXP Semiconductors

Electrical Characteristics

Figure 22. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1

4.5.2.1.4

DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3

There are two cases when the memory provides both read data and the read strobe in DDR mode:

•

B1—Memory generates both read data and read strobe on SCK edge

•

B2—Memory generates read data on SCK edge and generates read strobe on SCK2

edge

Table 42. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1

Symbol

Parameter

Min

Max

Unit

Frequency of operation

—

MHz

TIS

Setup time for incoming data

—

TIH

Hold time for incoming data

—

Table 43. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B1)

Symbol

Parameter

Min

Max

Unit

Frequency of operation

—

166

MHz

TSCKD

Time from SCK to data valid

—

TSCKDQS

Time from SCK to DQS

—

TSCKD - TSCKDQS

Time delta between TSCKD and TSCKDQS

-1

TIS

TIH

TIS

TIH

SCLK

SIO[0:7]

Internal Sample Clock

PIMXRT201VCFP4A Datasheet(PDF) 54 Page - NXP Semiconductors

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