PIMXRT201VCFP4A datasheet(70/119 Pages) NXP

70 / 119 page

i.MX RT1060 Crossover Processors for Consumer Products, Rev. 4, 04/2024

NXP Semiconductors

Electrical Characteristics

4.9

Communication interfaces

The following sections provide the information about communication interfaces.

4.9.1

LPSPI timing parameters

The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and

slave operations. Many of the transfer attributes are programmable. The following tables provide timing

characteristics for classic LPSPI timing modes.

All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as well as input

signal transitions of 3 ns and a 30 pF maximum load on all LPSPI pins.

Analog comparator hysteresis1

• CR0[HYSTCTR] = 00

—

• CR0[HYSTCTR] = 01

—

• CR0[HYSTCTR] = 10

—

108

• CR0[HYSTCTR] = 11

—

184

VCMPOH

Output high

VDD - 0.5

—

VCMPOI

Output low

—

0.5

tDHS

Propagation delay, high-speed

mode (EN = 1, PMODE = 1)2

—

tDLS

Propagation delay, low-speed

mode (EN = 1, PMODE = 0)2

—

tDInit

Analog comparator initialization

delay3

—

1.5

—



IDAC6b

6-bit DAC current adder (enabled) —

—



RDAC6b

6-bit DAC reference inputs

—

VDD

—

INLDAC6b

6-bit DAC integral non-linearity

-0.3

—

0.3

LSB4

DNLDAC6b

6-bit DAC differential non-linearity -0.15

—

0.15

LSB4

1 Typical hysteresis is measured with input voltage range limited to 0.7 to VDD - 0.7 V in high speed mode.

2 Signal swing is 100 mV.

3 Comparator initialization delay is defined as the time between software writes to the enable comparator module and the

comparator output setting to a stable level.

4 1 LSB = Vreference / 64

Table 56. Comparator and 6-bit DAC electrical specifications (continued)

Symbol

Description

Min.

Typ.

Max.

Unit

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