P4C1256L datasheet(1/11 Pages) PYRAMID

Part #	P4C1256L

Description	LOW POWER 32K x 8 STATIC CMOS RAM

PDF	11 Pages

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Manufacturer	PYRAMID [Pyramid Semiconductor Corporation]

Direct Link	http://www.pyramidsemiconductor.com

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1

Document # SRAM121 REV E

Revised June 2007

V

CC Current (Commercial/Industrial)

— Operating: 70mA/85mA

— CMOS Standby: 100µA/100µA

Access Times

—55/70 (Commercial or Industrial)

Single 5 Volts ±10% Power Supply

Easy Memory Expansion Using

CE

CE and OE

OE

Inputs

locations are specified on address pins A

0 to A14. Read-

ing is accomplished by device selection (

CE and output

enabling (

OE) while write enable (WE) remains HIGH.

By presenting the address under these conditions, the

data in the addressed memory location is presented on

the data input/output pins. The input/output pins stay in

the HIGH Z state when either

CE or OE is HIGH or WE

is LOW.

Package options for the P4C1256L include 28-pin 600

mil DIP, 28-pin 300 mil CERDIP, and 28-pin 300 mil Nar-

row Body SOP packages.

P4C1256L

LOW POWER 32K x 8

STATIC CMOS RAM

Common Data I/O

Three-State Outputs

Fully TTL Compatible Inputs and Outputs

Advanced CMOS Technology

Automatic Power Down

Packages

—28-Pin 600 mil DIP

—28-Pin 300 mil CERDIP

—28-Pin 300 mil Narrow Body SOP

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

DESCRIPTION

The P4C1256L device provides asynchronous opera-

tion with matching access and cycle times. Memory

FEATURES

The P4C1256L is a 262,144-bit low power CMOS

static RAM organized as 32Kx8. The CMOS memory

requires no clocks or refreshing, and has equal access

and cycle times. Inputs are fully TTL-compatible. The

RAM operates from a single 5V±10% tolerance power

supply.

Access times of 55 ns and 70 ns are available. CMOS

is utilized to reduce power consumption to a low level.

DIP (P6, D5-2), SOP (S11-3)

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