CY2037
Document #: 38-07354 Rev. *D
Page 7 of 10
Output Clock Switching Characteristics Over the Operating Range[6]
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
t1w
Output Duty Cycle at
1.4V, VDD = 4.5–5.5V
t1w = t1A ÷ t1B
1–40 MHz, CL <=50 pF
40–66 MHz, CL <=15 pF
66–125 MHz, CL <=25 pF
125–133 MHz, CL <=15 pF
45
45
40
40
55
55
60
60
%
%
%
%
t1x
Output Duty Cycle at
VDD/2, VDD = 4.5–5.5V
t1x = t1A ÷ t1B
1–66.6 MHz, CL <=25 pF
66.6–125 MHz, CL <=25 pF
125–133 MHz, CL <=15 pF
45
40
40
55
60
60
%
%
%
t1y
Output Duty Cycle at
VDD/2, VDD = 3.0–3.6
t1y = t1A ÷ t1B
1–40 MHz, CL <=30 pF
40–100 MHz, CL <=15 pF
45
40
55
60
%
%
t1z
Output Duty Cycle at
VDD/2, VDD = 2.7–3.0
t1y = t1A ÷ t1B
1–40 MHz, CL <=15 pF
40–66.6 MHz, CL <=10 pF
40
40
60
60
%
%
t2
Output Clock Rise Time Between 0.8V–2.0V, VDD = 4.5V–5.5V, CL = 50 pF
Between 0.8V–2.0V, VDD = 4.5V–5.5V, CL = 25 pF
Between 0.8V–2.0V, VDD = 4.5V–5.5V, CL = 15 pF
Between 0.2VDD–0.8VDD, VDD = 4.5V–5.5V, CL = 50 pF
Between 0.2VDD–0.8VDD, VDD = 3.0V–3.6V, CL = 30 pF
Between 0.2VDD–0.8VDD, VDD = 2.7V–3.6V, CL = 15 pF
1.8
1.2
0.9
3.4
4.0
2.4
ns
ns
ns
ns
ns
ns
t3
Output Clock Fall Time
Between 0.8V–2.0V, VDD = 4.5V–5.5V, CL = 50 pF
Between 0.8V–2.0V, VDD = 4.5V–5.5V, CL = 25 pF
Between 0.8V–2.0V, VDD = 4.5V–5.5V, CL = 15 pF
Between 0.2VDD– 0.8VDD, VDD = 4.5V-5.5V, CL = 50 pF
Between 0.2VDD– 0.8VDD, VDD = 3.0V–3.6V, CL = 30 pF
Between 0.2VDD– 0.8VDD, VDD = 2.7V–3.6V, CL = 15 pF
1.8
1.2
0.9
3.4
4.0
2.4
ns
ns
ns
ns
ns
ns
t4
Start-up Time Out of
Power D own
PD# pin LOW to HIGH[7]
12
ms
t5a
Power Down Delay Time
(synchronous setting)
PD# pin LOW to output LOW
(T = period of Output clk)
T/2
T+10
ns
t5b
Power Down Delay Time
(asynchronous setting)
PD# pin LOW to output LOW
10
15
ns
t6
Power Up Time
From power on[7]
12
ms
t7a
Output Disable Time
(synchronous setting)
OE pin LOW to output Hi-Z
(T = period of output clk)
T/2
T+10
ns
t7b
Output Disable Time
(asynchronous setting)
OE pin LOW to output Hi-Z
10
15
ns
t8
Output Enable Time
(always synchronous
enable)
OE pin LOW to HIGH
(T = period of output clk)
T1.5T+2
5
ns
t9
Peak-to-Peak Period
Jitter
VDD = 4.5V–5.5V, Fo > 33 MHz, VCO > 100 MHz
VDD = 2.7V–3.6V, Fo > 33 MHz, VCO > 100 MHz
VDD = 2.7V–5.5V, Fo < 33 MHz
±100
±125
±250
±125
±200
1% of
FO
ps
ps
ps
Notes
6. Not all parameters measured in production testing.
7. Oscillator start time cannot be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70 ohms.
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