PM7339 datasheet(21/81 Pages) PMC

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PM7339 S/UNI-CDB

DATASHEET

PMC-2000313

ISSUE 2

SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 19

Pin Name

Type

Pin No.

Function

RPOHCLK[4]

RPOHCLK[3]

RPOHCLK[2]

RPOHCLK[1]

Output

W13

U10

Receive PLCP Overhead Clock

(RPOHCLK[4:1]). RPOHCLK[4:1] is active

when PLCP processing is enabled. The

frequency of this signal depends on the

selected PLCP format. RPOHCLK[4:1] is

nominally a 26.7 kHz clock for a DS1

PLCP frame and a 33.7 kHz clock for an

E1 based PLCP frame. RPOHFP[4:1] and

RPOH[4:1] are updated on the falling edge

of RPOHCLK[4:1].

LCD[4]

LCD[3]

LCD[2]

LCD[1]

Output

Y14

W10

Loss of Cell Delineation (LCD[4:1]).

LCD[4:1] is an active high signal which is

asserted while the ATM cell processor has

detected a Loss of Cell Delineation defect.

FRMSTAT[4]

FRMSTAT[3]

FRMSTAT[2]

FRMSTAT[1]

Output

Framer Status (FRMSTAT[4:1]).

FRMSTAT[4:1] is an active high signal

which can be configured to show when the

PLCP framer has detected certain

conditions. The FRMSTAT[4:1] outputs

can be programmed via the STATSEL[2:0]

bits in the S/UNI-CDB Configuration 2

PLCP Out of Frame, AIS, and Loss of

Signal. FRMSTAT[4:1] should be treated

as a glitch free asynchronous signal.

ATM8

Input

L18

ATM Interface Bus Width Selection

(ATM8). The ATM8 input pin determines

whether the S/UNI-CDB works with a 8-bit

wide interface (RDAT[7:0] and TDAT[7:0])

or a 16-bit wide interface (RDAT[15:0] and

TDAT[15:0]). If ATM8 is set to logic 1,

then the 8-bit wide interface is chosen. If

ATM8 is set to logic 0, then the 16-bit wide

interface is chosen.

PM7339 Datasheet(PDF) 21 Page - PMC-Sierra, Inc

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