CYRF6936
Document #: 38-16015 Rev. *G
Page 19 of 40
Mnemonic
PWR_CTRL_ADR
Address
0x0B
Bit
7
6
5
4
3
2
1
0
Default
1
0
1
-
0
0
0
0
Read/Write
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
Function
PMU EN
LVIRQ EN
PMU Mode
Force
PFET Disable
LVI TH
PMU OUTV
Bit 7
Power Management Unit (PMU) Enable. Setting this bit enables the PMU only if PMU Mode Force (bit 5) is set. Otherwise it
has no effect. See PMU Mode Force (bit 5) description for more information.
Bit 6
Low Voltage Interrupt Enable. Setting this bit enables the LV IRQ interrupt. When this interrupt is enabled, if the VBAT voltage
falls below the threshold set by LVI TH, a low voltage interrupt is generated. The LVI is not available when the device is in sleep
mode. The LVI event on IRQ pin is automatically disabled whenever the PMU is disabled.
Bit 5
PMU Mode Force. If this bit is set, the PMU operation is based on the state of the PMU Enable Bit (bit 7). if this bit is not set
then the PMU is disabled in Sleep mode and enabled when not in Sleep mode, if Bit 7 = 1. If Bit 7 = 1 and Bit 5 = 1, PMU is
enabled always (even during sleep). If Bit 7 = 0 and Bit 5 = 1, PMU is disabled always. If Bit 7 = 1and Bit 5 = 0, PMU is disabled
only in Sleep Mode.
Bits 3:2
Low Voltage Interrupt Threshold. This field sets the voltage on VBAT at which the LVI is triggered. 11 = 1.8V; 10 = 2.0V;
01 = 2.2V; 00 = PMU OUTV voltage.
Bits 1:0
PMU Output Voltage. This field sets the minimum output voltage of the PMU. 11 = 2.4V; 10 = 2.5V; 01 = 2.6V; 00 = 2.7V. When
the PMU is active, the voltage output by the PMU on VREG is never less than this voltage, provided that the total load on the
VREG pin is less than the specified maximum value, and the voltage in VBAT is greater than the specified minimum value.
The order of writing these bits impacts the value of the Sleep current ISB.
Mnemonic
XTAL_CTRL_ADR
Address
0x0C
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
-
-
1
0
0
Read/Write
R/W
R/W
R/W
-
-
R/W
R/W
R/W
Function
XOUT FN
XSIRQ EN
Not Used
Not Used
FREQ
Bits 7:6
XOUT Pin Function. This field selects between the different functions of the XOUT pin. 00 = Clock frequency set by XOUT
FREQ; 01 = Active LOW PA Control; 10 = Radio data serial bit stream. If this option is selected and SPI is configured for 3-wire
mode then the MISO pin outputs a serial clock associated with this data stream; 11 = GPIO. To disable this output, set to GPIO
mode, and set the GPIO state in IO_CFG_ADR.
Bit 5
Crystal Stable Interrupt Enable. This bit enables the OS IRQ interrupt. When enabled, this interrupt generates an IRQ event
when the crystal has stabilized after the device has awaken from sleep mode. This event is cleared by writing ‘0’ to this bit.
Bits 2:0
XOUT Frequency. This field sets the frequency output on the XOUT pin when XOUT FN is set to 00. 0 = 12 MHz; 1 = 6 MHz,
2 = 3 MHz, 3 = 1.5 MHz, 4 = 0.75 MHz; other values are not defined.
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