STAR1000
Document Number: 38-05714 Rev. *B
Page 9 of 21
Timing and Control Signals
The pixels addressing is done by direct addressing of rows
and columns. This approach has the advantage of full flexibility
when accessing the pixel array: multiple windowing and
subsampled read out are possible by proper programming.
The following paragraphs clarify the timing for row and column
readout.
Row Selection and Reset Timing
Figure 5. shows the timing of the line sequence control signals.
The timing constraints are presented in Table 6.
The address, presented at the address IO pins (A0…A9) is
latched in with the LD-Y pulse (active low). After latching; the
external controller already produces a new address.
Figure 5. Line Selection and Reset Sequence
Latching in a Y- address selects the addressed row and
connects the pixel outputs of that row to the column amplifiers.
Through the sequence of the S and R pulse and the reset
pulse in between the pixel output signal and reset level are
sampled and produced at the output of the column amplifier
(to do the FPN double sampling correction).
At this time horizontal read out of the selected row is started
and another row is reset to effectuate reduced integration time
(electronic rolling shutter).
A0......A9
LD_Y
INTERNAL
S
RESET
R
CAL
(Once each
frame)
ROW
READOUT
Read Address
Reset Address
k
l
m
k
l
m
Row Selected for Readout
Row Selected for Reset
a
b
c
d
e
b
hi
f
d
g
Time Available for Readout of Row Y-1
Idle
Time Available for X-readout of Row Y
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