PM7388

Preliminary

Frame Engine and Datalink Manager

FREEDM 336A1024

PMC-1991475 (p2)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

 Copyright PMC-Sierra, Inc. 2001

FEATURES

• Single-chip multi-channel packet

processor supporting line rate

throughput transfers of packet sizes

from 40 to 9.6 Kbytes, for up to an

aggregate of 336 T1s, 252 E1s, or 12

DS-3s.

• Provides simultaneous support of

PPP, Frame Relay, Multilink-PPP and

Multilink-Frame Relay protocols.

Alternative protocols supported via

HDLC termination and full packet store

of the data within the HDLC structure.

MULTILINK PPP AND FRAME

RELAY BUNDLES

• Capable of supporting fragment sizes

from 1 to 9.6 Kbytes.

• Support for 3 egress fragmentation

sizes (128, 256, and 512 bytes)

configurable on a per multilink bundle.

Optionally full packet transfers are

supported on a per bundle basis.

• Supports up to 168 multilink bundles

with up to 12 member links per bundle.

These bundles are composed of

independent HDLC channels.

• Support for up to 100 ms of intra

bundle skew in the receive direction

when supporting the minimum.

fragment size.

• Support for PPP header compression

as per RFC 1661.

PPP

• Support for 16 COS levels in

accordance with RFC 2686.

• Either 12 bit or 24 bit sequence

number, with short and long fragment

header formats, is supported.

• Link Control protocol packets are

identified by the PID as control

protocols and will be forwarded to the

Any-PHY interface.

FRAME RELAY

• Link layer address lookup can be

performed based on HDLC channel

and 10 bit DLCI for HDLC channels

supporting Frame Relay protocols.

• The lookup algorithm can support a

maximum of 16 K connection

identifiers (CIs) amongst multilink FR

bundles. The connection identifiers

are ignored in singlelink FR channels.

• Control frames are identified and

forwarded to Any-PHY interface.

• 12 bit sequence numbers supported.

• FECN, BECN, and DE ingress

processing as per FRF.12.

Rx ANY-PHY

I/F

(RAPI-12)

RXCLK

RVAL

RSX

RSOP

REOP

RMOD

RXDATA[15:0]

RXPRTY

RENB

RPA

RXADDR[3:0]

RERR

SRAM

Controller

(SRAMC)

CCDAT[35:0]

CCBSELB[1:0]

CCWEB

CCADD[17:0]

CCSELB

CB DRAM

Controller

(CB_DRAMC)

CBDAT[47:0]

CBRASB

CBWEB

CBADD[12:0]

CBCSB

CBCASB

CBBS[1:0]

Microprocessor I/F (BUMP2)

Tx

Fragment

Builder

(TFRAG)

Tx ANY-PHY

I/F (TAPI-12)

TXCLK

TEOP

TMOD

TERR

TRDY

TSX

TXPRTY

TXDATA[15:0]

TPA

TXADDR[15:0]

Egress

Queue

Manager

(EQM-12)

Ingress

Queue

Manager

(EQM-12)

Frame

Builder

(FRMBLD)

Rx

Fragment

Builder

(RFRAG)

RS DRAM

Controller

(RS_DRAMC)

Rx HDLC

Processor /

Partial Packet

Buffer

(RHDL-12)

Performance

Monitor

(PM-12)

Extract

SBI

(EXSBI-

336)

DC1FP

DV5

DPL

DDP

DDATA[7:0]

Tx HDLC

Processor /

Partial Packet

Buffer

(THDL-12)

Receive

Channel

Assigner

(RCAS-12)

JTAG

Insert

SBI

(INSBI-

336)

AJUST_REQ

AV5

APL

ADP

ADATA[7:0]

CIFPOUT

ACIFP

Transmit

Channel

Assigner

(TCAS-12)

REFCLK

Data

Control

DDLL-

140

BLOCK DIAGRAM