PM8355

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4-Channel 2.125, 2.5 and 3.125 Gbit/s Transceiver with Half-rate Support

QuadPHY-II™

PMC-2000791 (A4)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

© Copyright PMC-Sierra, Inc. 2001

GENERAL DESCRIPTION

The QuadPHY-II is a physical layer

transceiver ideal for systems requiring

high speed point-to-point communi-

cation links. It is applicable for PMA-

PMD connections in 10 GE, Infiniband 1

or 4 x 2.5 Gbit/s links, 1 and 2 Gbit/s

Fibre Channel, as well as high speed

serial backplanes for high capacity

systems.

FEATURES

GENERAL

• 10Gbit/s, bi-directional, XAUI to XGMII

link supporting the proposed IEEE

802.3ae (the standard is draft and is

subject to change).

• Four independent 2.125, 2.5 and 3.125

Gbit/s Serdes for Fibre Channel,

Infiniband, 10 GE line cards and high-

speed backplane applications.

• Half/Full rate mode selectable per

channel.

• Integrated serializer/ deserializer, clock

synthesis, clock recovery and 8B/10B

encode/decode logic.

• Under 2 Watts typical power.

SERIAL I/O

• Redundant high speed serial I/O

channels for convenient switching to

redundant fabric.

• High speed outputs with optional pre-

emphasis to drive longer backplanes.

• High speed I/O with on-chip

termination resistors to directly drive

dual-terminated 50 Ohm lines.

PARALLEL I/O

• 10-bit Dual Data Rate (DDR) parallel

interface.

• Selectable source simultaneous or

source synchronous transmit and

receive parallel interfaces.

• Convenient output clock for user

friendly ASIC timing.

• Interoperates with SSTL2 and 1.8V

LVCMOS standard.

TRUNKING &TIMING

• Integrated Receive FIFO synchronizes

incoming data to local clock domain.

• Trunking feature de-skews and aligns

all four channels to form a single 10

Gbit/s logical link.

TEST FEATURES

• Extensive control of loopback, BIST,

and operating modes via 802.3

compliant MDC/MDIO serial interface.

• On-chip packet generator/checker-

provides at-speed diagnostics.

• Built-in error counters per channel.

• Support for IEEE 1149.1 JTAG testing

on all pins.

PHYSICAL

• 1.8V, 0.18 micron standard CMOS

technology with 2.5V tolerant I/O.

• 289-ball PBGA (19mm x 19mm

package).

APPLICATIONS

• High speed serial backplanes

•10 GE links

• Fibre Channel transceivers

• Infiniband transceivers

• XAUI retimers

• Intra-system interconnect

8B/10B Encoder

Serializer

Transmit Channel A (1 of 4)

FIFO & Trunking

Logic

10B/8B Decoder

Deserialize & Byte

Align

Clock Recovery

Receive Channel A (1 of 4)

Clock Synthesizer

Common Control Logic

RESET,

MDC, MDIO

Mode strapping pins

JTAG interface

BIST pins

TXD[9:0]

9 or 10

10

RXCLK

(per channel)

RXD[9:0]

8 or 10

9 or 10

TXCLK

(shared)

FIFO & /A/

insert

Adaptive

Sampler

SYSCLK

(1x or 2x rate)

TDOXP/

TDOXN

TDOYP/

TDOYN

RDIXP/

RDIXN

RDIYP/

RDIYN

(per channel)

(per channel)

(per channel)

(per channel)

2

2

2

2

BLOCK DIAGRAM