®

32K X 8 BIT LOW POWER CMOS SRAM

PIN CONFIGURATION

A12

A7

A6

A5

A4

A3

A2

A1

A0

DQ0

DQ1

DQ2

Vss

A14

Vcc

A8

A9

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

PDIP/SOP

28

14

13

12

11

10

9

8

7

6

5

4

3

2

1

17

16

15

20

19

18

22

23

24

25

26

27

21

A13

CE#

OE#

WE#

sTSOP

DQ3

A11

A9

A8

A13

DQ2

A10

A14

A12

A7

A6

A5

Vcc

DQ7

DQ6

DQ5

DQ4

Vss

DQ1

DQ0

A0

A1

A2

A4

A3

AS6C62256

28

14

13

12

11

10

9

8

7

6

5

4

3

2

1

17

16

15

20

19

18

22

23

24

25

26

27

21

OE#

WE#

CE#

ABSOLUTE MAXIMUM RATINGS*

PARAMETER

SYMBOL

RATING

UNIT

-0.5 to 7.0

V

0 to 70(C grade)

T

e

r

u

t

a

r

e

p

m

e

T

g

n

it

a

r

e

p

O

A

-40 to 85(I grade)

T

e

r

u

t

a

r

e

p

m

e

T

e

g

a

r

o

t

S

STG

-65 to 150

P

n

o

it

a

p

i

s

s

i

D

r

e

w

o

P

D

1

W

I

t

n

e

r

r

u

C

t

u

p

t

u

O

C

D

OUT

50

mA

Soldering Temperature (under 10 sec)

260

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress

rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

TRUTH TABLE

MODE

CE#

OE#

WE#

I/O OPERATION

SUPPLY CURRENT

Standby

H

X

X

High-Z

Output Disable

L

H

H

High-Z

Read

L

L

H

Write

L

X

L

ºC

ºC

ºC

February 2007

AS6C62256

02/FEB/07, v1.0

Alliance Memory Inc.

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