SI5366 datasheet(11/20 Pages) SILABS

11 / 20 page

Si5366

Preliminary Rev. 0.2

DEC

LVCMOS

Coarse Latency Decrement.

A pulse on this pin decreases the input to output device latency

by 1/fOSC (approximately 200 ps). Detailed operations and tim-

ing characteristics for this pin may be found in the Any-Rate

Precision Clock Family Reference Manual. There is no limit on

the range of latency adjustment by this method. If both INC and

DEC are tied high, phase buildout is disabled and the device

maintains a fixed-phase relationship between the selected

input clock and the output clock during an input clock switch.

Detailed operations and timing characteristics for this pin may

be found in the Any-Rate Precision Clock Family Reference

Manual.

This pin has a weak pull-down.

INC

LVCMOS

Coarse Latency Increment.

A pulse on this pin increases the input to output device latency

by 1/fOSC (approximately 200 ps). Detailed operations and tim-

ing characteristics for this pin may be found in the Any-Rate

Precision Clock Family Reference Manual. There is no limit on

the range of latency adjustment by this method. If both INC and

DEC are tied high, phase buildout is disabled and the device

maintains a fixed-phase relationship between the selected

input clock and the output clock during an input clock switch.

Detailed operations and timing characteristics for this pin may

be found in the Any-Rate Precision Clock Family Reference

Manual.

This pin has a weak pull-down.

FOS_CTL

3-Level

Frequency Offset Control.

This pin enables or disables use of the CKIN2 FOS reference

as an input to the clock selection state machine.

L = FOS Disabled.

M = Stratum 3/3E FOS Threshold.

H = SONET Minimum Clock FOS Threshold.

This pin has a weak pull-down.

C1A

LVCMOS

CKIN1 Active Clock Indicator.

This pin serves as the CKIN1 active clock indicator.

0 = CKIN1 is not the active input clock.

1 = CKIN1 is currently the active input clock to the PLL.

C2A

LVCMOS

CKIN2 Active Clock Indicator.

This pin serves as the CKIN2 active clock indicator.

0 = CKIN2 is not the active input clock.

1 = CKIN2 is currently the active input clock to the PLL.

BWSEL0

BWSEL1

3-Level

Bandwidth Select.

These pins are three level inputs that select the DSPLL closed

loop bandwidth. Detailed operations and timing characteristics

for these pins may be found in the Any-Rate Precision Clock

Family Reference Manual.

Table 3. Si5366 Pin Descriptions (Continued)

Pin #

Pin Name

I/O

Signal Level

Description

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