CS42L51 datasheet(29/88 Pages) CIRRUS

29 / 88 page

DS679F1

CS42L51

4.3.2

High-Pass Filter and DC Offset Calibration

The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation

filter. If the high-pass filter is “frozen” during normal operation, the current value of the DC offset for the

corresponding channel is held. It is this DC offset that will continue to be subtracted from the conversion

result. This feature makes it possible to perform a system DC offset calibration by:

Running the CODECwith the high-pass filter enabled and the DC offset not “frozen” until the filter

settles. See the Digital Filter Characteristics for filter settling time.

Freezing the DC offset.

The high-pass filters are controlled using the ADCx_HPFRZ and ADCx_HPFEN bits.

If a particular ADC channel is used to measure DC voltages, the high-pass filter may be disabled using

the ADCx_HPFEN bit.

4.3.3

Digital Routing

The digital output of the ADC may be internally routed to the signal processing engine (SPE) for playback

of analog input signals. Volume to the DAC may be controlled using the ADCMIX[6:0] bits. The serial input

data may also be routed to the ADC serial interface using the DIGMIX bit. This is useful for recording a

digital mix along with the analog input.

4.3.4

Differential Inputs

The stereo pair inputs act as a single differential input when the MICMIX bit is enabled. This provides com-

mon mode rejection of noise in digitally intense PCB’s where the microphone signal traverses long traces,

or across long microphone cables as illustrated in Figure 9.

Since the mixer provides a differential combination of the two signals, the potential input mix may exceed

the maximum full-scale input and result in clipping. The level out of the mixer, therefore, is automatically

attenuated 6 dB. Gain may be applied using either the analog PGA or MIC Pre-amp or the digital ADCMIX

volume control to re-adjust a small signal to desired levels.

The analog inputs may also be used as a differential input pair as illustrated in Figure 10. The two chan-

nels are differentially combined when the MICMIX bit is enabled.

4.3.4.1

External Passive Components

The microphone input is internally biased to VQ. Input signals must be AC coupled using external capaci-

tors with values consistent with the desired high-pass filter design. The MICINx input resistance of 50 k

Ω

may be combined with an external capacitor of 1

µF to achieve the cutoff frequency defined by the equa-

tion,

An electrolytic capacitor must be placed such that the positive terminal is positioned relative to the side with

the greater bias voltage. The MICBIAS voltage level is controlled by the MICBIAS_LVL[1:0] bits.

Software

Controls:

“ADC Control (Address 06h)” on page 54.

Software

Controls:

“ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh)” on page 61, “Inter-

face Control (Address 04h)” on page 52.

CS42L51 Datasheet(PDF) 29 Page - Cirrus Logic

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