CS42L51 datasheet(40/88 Pages) CIRRUS

40 / 88 page

DS679F1

CS42L51

4.5.3

High-Impedance Digital Output

The serial port may be placed on a clock/data bus that allows multiple masters for the serial port I/O with-

out the need for external buffers. The 3ST_SP bit places the internal buffers for these I/O in a high-imped-

ance state, allowing another device to transmit serial port data without bus contention.

4.5.4

Quarter- and Half-Speed Mode

Quarter-Speed Mode (QSM) and Half-Speed Mode (HSM) allow lower sample rates while maintaining a

relatively flat noise floor in the typical audio band of 20 Hz - 20 kHz. Single-Speed Mode (SSM) will allow

lower frequency sample rates; however, the DAC's noise floor, that normally rises out-of-band, will scale

with the lower sample rate and begin to rise within the audio band. QSM and HSM corrects for most of

this scaling, effectively increasing the dynamic range of the CODEC at lower sample rates, relative to

SSM.

4.6

Digital Interface Formats

The serial port operates in standard I²S, Left-Justified or Right-Justified (DAC only) digital interface formats

with varying bit depths from 16 to 24. Data is clocked out of the ADC or into the DAC on the rising edge of

SCLK. Figures 19-21 illustrate the general structure of each format. Refer to “Switching Specifications - Se-

rial Port” on page 20 for exact timing relationship between clocks and data.

Software

Control:

“Interface Control (Address 04h)” on page 52.

Hardware

Control:

Setting

Selection

“I²S/LJ” pin 3

Left-Justified Interface

I²S Interface

CS42L51

Transmitting Device #1

Transmitting Device #2

Receiving Device

3ST_SP

SDOUT

SCLK/LRCK

Figure 18. Tri-State Serial Port

LRCK

SCLK

MS B

LS B

MS B

LS B

AOUTA / AINxA

L e ft C h an ne l

R ig h t C han ne l

SDIN

AOUTB / AINxB

MSB

Figure 19. I²S Format

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