Rev 1.1, May 29, 2007
Page 7 of 12
SL2309
Switching Specifications: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades
Symbol
Description
Condition
Min
Typ
Max
Unit
High drive (-1H). All outputs CL=15pF
10
–
140
MHz
High drive (-1H), All outputs CL=30pF
10
–
100
MHz
Standard drive, (-1), All outputs CL=15pf
10
–
100
MHz
FMAX1
Maximum Frequency
[1]
(Input=Output )
All Active PLL Modes
Standard drive, (-1), All outputs CL=30pf
10
–
66
MHz
High drive (-1H). All outputs CL=15pF
0
–
140
Notes:
1. For the given maximum loading conditions. See CL in Operating Conditions Table.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
MHz
High drive (-1H), All outputs CL=30pF
0
–
100
MHz
Standard drive, (-1), All outputs CL=15pf
0
–
100
MHz
FMAX2
Maximum Frequency
[1]
(Input=Output )
PLL Bypass Mode
(S2=1 and S1=0)
Standard drive, (-1), All outputs CL=30pf
0
–
66
MHz
INDC
Input Duty Cycle
Measured at 1.4V, Fout=66MHz, CL=15pF
30
50
70
%
OUTDC
Output Duty Cycle
[2]
Measured at 1.4V, Fout=66MHz, CL=15pF
40
50
60
%
High drive (-1H), CL=15pF
–
–
1.5
ns
High drive (-1H), CL=30pF
–
–
1.8
ns
Standard drive (-1), CL=15pF
–
–
2.2
ns
tr/f
Rise, Fall Time (3.3V)
[2]
(Measured at: 0.8 to 2.0V)
Standard drive (-1), CL=30pF
–
–
2.5
ns
t1
Output-to-Output Skew
[2]
All outputs CL=0 or equally loaded, -1 or
-1H drives
–
50
120
ps
(Measured at VDD/2)
t2
Device-to-Device Skew
[2]
(Measured at VDD/2)
All outputs CL=0 or equally loaded, -1 or
-1H drives
–
150
400
ps
PLL Bypass mode
Only when S2=1 and S1=0
1.5
5
8.7
ns
t3
Delay Time, CLKIN Rising
Edge to CLKOUT Rising
Edge
[2]
(Measured at VDD/2)
PLL enabled
–150
–
150
ps
All active PLL modes
PLL Lock Time
[2]
tPLOCK
Time from 90% of VDD to valid clocks on
all the output clocks
–
–
1.0
ms
Fin=Fout=66 MHz, <CL=15pF, -1H drive
–
50
100
ps
CCJ
Cycle-to-cycle Jitter
[2]
Fin=Fout=66 MHz, <CL=15pF, -1 drive
–
60
120
ps
Fin=Fout=66 MHz, <CL=30pF, -1H drive
–
65
130
ps
Fin=Fout=66 MHz, <CL=30pF, -1 drive
–
75
150
ps
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