CE81 Series

2

(Continued)

• Hierarchical design environment for supporting large-scale circuits

• Simulation (before layout) considering the input slew rate and detailed RC delay calculation (after layout) ,

supporting development with minimized timing trouble after trial manufacture

• Support for memory (RAM/ROM) SCAN

• Support for memory (RAM) BIST

• Support for boundary SCAN

• Support for path delay test

• A variety of package options

(TQFP, HQFP, EBGA, FBGA, TAB-BGA, LQFP)

■ MACRO LIBRARY (Including macros being prepared)

1.

Logic cells (about 800 types)

2.

IP macros

3.

Special I/O interface macros

• Adder

• Decoder

•AND-OR Inverter

•Non-SCAN Flip Flop

•Clock Buffer

•Inverter

•Latch

•Buffer

• NAND

• OR-AND Inverter

•AND

•OR

•NOR

•Selector

• SCAN Flip Flop

• BUS Driver

•ENOR

• EOR

•AND-OR

•Others

CPU/DSP

FR, SPARClite, standard CPU (under preparation)

Communications DSP, DSP for AV

Interface macro

PCI, IEEE1394, USB, IrDA, etc.

Multimedia processing macros

JPEG, MPEG, etc.

Mixed signal macros

ADC, DAC, OPAMP, etc.

Compiled macros

RAM, ROM, multiplier, adder, multiplier-accumulator, etc.

PLL

Analog PLL, digital PLL

• T-LVTTL

• SSTL

• HSTL

• P-CML

• LVDS

• PCI

• AGP

• USB

• IEEE1394