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DDP3300A Datasheet(PDF) 22 Page - Micronas |
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DDP3300A Datasheet(HTML) 22 Page - Micronas |
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22 / 53 page ![]() DDP 3300 A PRELIMINARY DATA SHEET MICRONAS INTERMETALL 22 3. Serial Interface 3.1. I2C-bus Interface Communication between the DDP 3300 A and the ex- ternal controller is done via I2C-bus. The DDP 3300 A has an I2C-bus slave interface and uses I2C clock syn- chronization to slow down the interface if required. The I2C-bus interface uses one level of subaddress: one I2C- bus address is used to address the IC and a subaddress selects one of the internal registers. The I2C-bus chip address is given below: Note: The I2C address is subject to change! A6 A5 A4 A3 A2 A1 A0 R/W 1 0 0 0 1 0 1 0/1 The registers of the DDP 3300 A have 8 or 16-bit data size; 16-bit registers are accessed by reading/writing two 8-bit data words. Functions implemented by firmware in the on-chip con- trol microprocessor (FP) located in the VPC are ex- plained in the VPC datasheet. Figure 3–1 shows I2C-bus protocols for read and write operations of the interface; the read operation requires an extra start condition and repetition of the chip address with read command set. WP 1 or 2 byte data W high byte data S S Ack Ack Ack Ack 0111 1100 0111 1100 R S Ack SDA SCL 1 0 SP P low byte data Ack W= 0 R= 1 Ack = 0 Nak= 1 S = Start P = Stop Ack Nak Fig. 3–1: I2C-bus protocols 1000 101 1000 101 1000 101 I2C read access subaddress 7c Example: I2C read access subaddress 7c 3.2. Control and Status Registers Table 3–1 gives definitions of the DDP 3300 A control and status registers. The number of bits indicated for each register in the table is the number of bits imple- mented in hardware, i.e., a 9-bit register must always be accessed using two data bytes, but the 7 MSB will be don’t care on write operations and 0 on read operations. Write registers that can be read back are indicated in the following table. A hardware reset initializes all control registers to 0. The automatic chip initialization loads a selected set of regis- ters with the default values given in Table 3–1. The register modes given in Table 3–1 are: w write only register w/r write/read data register r read data from DDP 3300 A h register is latched with horizontal pulse v register is latched with vertical pulse The mnemonics used in the INTERMETALL DDP 3300 A demo software are given in the last column. |
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