AT89C52 datasheet(12/23 Pages) SYC

12 / 23 page

AT89C52

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively,

of an inverting amplifier that can be configured for use as

an on-chip oscillator, as shown in Figure 7. Either a quartz

crystal or ceramic resonator may be used. To drive the

device from an external clock source, XTAL2 should be left

unconnected while XTAL1 is driven, as shown in Figure 8.

There are no requirements on the duty cycle of the external

clock signal, since the input to the internal clocking circuitry

is through a divide-by-two flip-flop, but minimum and maxi-

mum voltage high and low time specifications must be

observed.

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-

chip peripherals remain active. The mode is invoked by

software. The content of the on-chip RAM and all the spe-

cial functions registers remain unchanged during this

mode. The idle mode can be terminated by any enabled

interrupt or by a hardware reset.

Note that when idle mode is terminated by a hardware

reset, the device normally resumes program execution

from where it left off, up to two machine cycles before the

internal reset algorithm takes control. On-chip hardware

inhibits access to internal RAM in this event, but access to

the port pins is not inhibited. To eliminate the possibility of

an unexpected write to a port pin when idle mode is termi-

nated by a reset, the instruction following the one that

invokes idle mode should not write to a port pin or to exter-

nal memory.

Power-down Mode

In the power-down mode, the oscillator is stopped, and the

instruction that invokes power-down is the last instruction

executed. The on-chip RAM and Special Function Regis-

ters retain their values until the power-down mode is

terminated. The only exit from power-down is a hardware

reset. Reset redefines the SFRs but does not change the

on-chip RAM. The reset should not be activated before V

is restored to its normal operating level and must be held

active long enough to allow the oscillator to restart and

stabilize.

Figure 7. Oscillator Connections

Note:

C1, C2 = 30 pF

± 10 pF for Crystals

= 40 pF

± 10 pF for Ceramic Resonators

Figure 8. External Clock Drive Configuration

XTAL2

GND

XTAL1

XTAL2

XTAL1

GND

EXTERNAL

OSCILLATOR

SIGNAL

Status of External Pins During Idle and Powe-down Modes

Mode

Program Memory

ALE

PSEN

PORT0

PORT1

PORT2

PORT3

Idle

Internal

Data

Idle

External

Float

Data

Address

Data

Power-down

Internal

Data

Power-down

External

Float

Data

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