PDTC144WM

50 V, 100 mA NPN resistor-equipped

transistor; R1 = 47 kΩ, R2 = 22 kΩ

18 October 2024

Product data sheet

1. General description

NPN Resistor-Equipped Transistor (RET) in an leadless ultra small SOT883 (SC-101) Surface-

Mounted Device (SMD) plastic package.

PNP complement: PDTA144WM

2. Features and benefits

• Built-in bias resistors

• Simplifies circuit design

• Reduces component count

• Reduces pick and place costs

• AEC-Q101 qualified

3. Applications

• General purpose switching and amplification

• Inverter and interface circuits

• Circuit applications

4. Quick reference data

Table 1. Quick reference data

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VCEO

collector-emitter

voltage

open base

-

-

50

V

IO

output current

-

-

100

mA

R1

bias resistor 1 (input)

33

47

61

kΩ

R2/R1

bias resistor ratio

Tamb = 25 °C

0.37

0.47

0.57

5. Pinning information

Table 2. Pinning information

Pin

Symbol

Description

Simplified outline

Graphic symbol

1

I

input (base)

2

GND

ground (emitter)

3

O

output (collector)

2

3

1

Transparent

top view

DFN1006-3 (SOT883)

sym007

O

GND

I

R1

R2