AD7949 datasheet(11/20 Pages) AD

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Preliminary Technical Data

AD7689

Rev. PrC | Page 11 of 20

THEORY OF OPERATION

SW+

MSB

16,384C

IN+

LSB

COMP

CONTROL

LOGIC

SWITCHES CONTROL

BUSY

OUTPUT CODE

CNV

CAP

GND

IN- or

COM

32,768C

SW–

MSB

16,384C

LSB

32,768C

Figure 11. ADC Simplified Schematic

OVERVIEW

The AD7689 is an 8-channel, 16-bit, charge redistribution

successive approximation register (SAR), analog-to-digital

converter (ADC). The AD7689 is capable of converting 250,000

samples per second (250 kSPS) and powers down between

conversions. For example, when operating with an external

reference at 1 kSPS, it consumes TBD μW typically, ideal for

battery-powered applications.

The AD7689 contains all of the components for use in a multi-

channel, low power, data acquisition system including:

• 16-bit SAR ADC with no missing codes

• 8-channel, low crosstalk multiplexer

• Internal low drift reference and buffer

• Temperature sensor

• Selectable 1-pole filter

• Channel sequencer

all of which are configured through a SPI compatible, 14-bit

The AD7689 provides the user with an on-chip track-and-hold

and does not exhibit pipeline delay or latency.

The AD7689 uses a simple SPI interface for configuring and

receiving conversion results.

The AD7689 is specified from 2.3 V to 5.5 V and can be

interfaced to any 1.8 V to 5 V digital logic family. It is housed in

a 20-lead, 4mm x 4mm LFCSP that combines space savings and

allows flexible configurations. It is pin-for-pin compatible with

the 16-bit AD7682, AD7699 and 14-bit AD7949.

CONVERTER OPERATION

The AD7689 is a successive approximation ADC based on a

charge redistribution DAC. Figure 11 shows the simplified

schematic of the ADC. The capacitive DAC consists of two

identical arrays of 16 binary-weighted capacitors, which are

connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the

comparator’s input are connected to GND via SW+ and SW−.

All independent switches are connected to the analog inputs.

Thus, the capacitor arrays are used as sampling capacitors and

acquire the analog signal on the IN+ and IN− (or COM) inputs.

When the acquisition phase is complete and the CNV input

goes high, a conversion phase is initiated. When the conversion

phase begins, SW+ and SW− are opened first. The two

capacitor arrays are then disconnected from the inputs and

connected to the GND input. Therefore, the differential voltage

between the IN+ and IN- (or COM) inputs captured at the end

of the acquisition phase is applied to the comparator inputs,

causing the comparator to become unbalanced. By switching

each element of the capacitor array between GND and CAP, the

comparator input varies by binary-weighted voltage steps

(VREF/2, VREF/4 ... VREF/32,768). The control logic toggles these

switches, starting with the MSB, to bring the comparator back

into a balanced condition. After the completion of this process,

the part returns to the acquisition phase, and the control logic

generates the ADC output code and a busy signal indicator.

Because the AD7689 has an on-board conversion clock, the

serial clock, SCK, is not required for the conversion process.

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