IR3081A

Soft Start, Over-Current Fault Delay, and Hiccup Mode

The IR3081A has a programmable soft-start function to limit the surge current during the converter start-up. A

capacitor connected between the SS/DEL and LGND pins controls soft start as well as over-current protection delay

and hiccup mode timing. A charge current of 70uA and discharge current of 6uA control the up slope and down

slope of the voltage at the SS/DEL pin respectively

Figure 10 depicts the various operating modes as controlled by the SS/DEL function. If there is no fault, the SS/DEL

pin will begin to be charged. The error amplifier output is clamped low until SS/DEL reaches 1.3V. The error

amplifier will then regulate the converter’s output voltage to match the SS/DEL voltage less the 1.3V offset until it

reaches the level determined by the VID inputs. The SS/DEL voltage continues to increase until it rises above 3.71V

and allows the PWRGD signal to be asserted. SS/DEL finally settles at 3.8V, indicating the end of the soft start.

Under Voltage Lock Out and VID=11111x faults as well as a low signal on the ENABLE input immediately sets the

fault latch causing SS/DEL to begin to discharge. The SS/DEL capacitor will continue to discharge down to 0.2V. If

the fault has cleared the fault latch will be reset by the discharge comparator allowing a normal soft start to occur.

A delay is included if an over-current condition occurs after a successful soft start sequence. This is required since

over-current conditions can occur as part of normal operation due to load transients or VID transitions. If an over-

current fault occurs during normal operation it will initiate the discharge of the capacitor at SS/DEL but will not set

the fault latch immediately. If the over-current condition persists long enough for the SS/DEL capacitor to discharge

below the 90mV offset of the delay comparator, the Fault latch will be set pulling the error amplifier’s output low

inhibiting switching in the phase ICs and de-asserting the PWRGD signal. The SS/DEL capacitor will continue to

discharge until it reaches 0.2V and the fault latch is reset allowing a normal soft start to occur. If an over-current

condition is again encountered during the soft start cycle the fault latch will be set without any delay and hiccup

mode will begin. During hiccup mode the charge to discharge current ratio results in a fixed 7.9% hiccup mode duty

cycle regardless of at what point the over-current condition occurs. However, the hiccup frequency is determined by

the load current and over-current set value.

The over-current delay can be reduced by adding a resistor in series with the SS/DEL capacitor. The delay

comparator’s offset voltage is reduced by the drop in the resistor caused by the discharge current. The value of the

series resistor should be 10KΩ or less to avoid interference with the soft start function.

If SS/DEL pin is pulled below 0.9V, the converter can be disabled.

Under Voltage Lockout (UVLO)

The UVLO function monitors the IR3081A’s VCC supply pin and ensures that IR3081A has a high enough voltage

to power the internal circuit. The IR3081A’s UVLO is set higher than the minimum operating voltage of compatible

Phase ICs thus providing UVLO protection for them as well. During power-up the fault latch is reset when VCC

exceeds 9.7V and there is no other fault. If the VCC voltage drops below 8.9V the fault latch will be set. For

converters using a separate 5V supply for gate driver bias an external UVLO circuit can be added to prevent any

operation until adequate voltage is present. A diode connected between the 5V supply and the SS/DEL pin provides

a simple 5V UVLO function.

Over Current Protection (OCP)

The current limit threshold is set by a resistor connected between the OCSET and VDAC pins. If the IIN pin voltage,

which is proportional to the average current plus DAC voltage, exceeds the OCSET voltage, the over-current

protection is triggered.

VID = 11111X Fault

VID codes of 111111 and 111110 will set the fault latch and disable the error amplifier. An 800ns delay is provided

to prevent a fault condition from occurring during Dynamic VID changes.

Enable Input

Pulling the ENABLE pin below 0.6V sets the Fault Latch.

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