S5935TFC datasheet(70/204 Pages) AMCC

70 / 204 page

S5935 – PCI Product

DS1527

AMCC Confidential and Proprietary

Revision 1.02 – June 27, 2006

Data Book

Table 32. Interrupt Control/Status Register

Bit

Description

31:24

FIFO and Endian Control.

Interrupt asserted. This read only status bit indicates that one or more of the four possible interrupt conditions is

present. This bit is nothing more than the ORing of the interrupt conditions described by bits 19 through 16 of this

Reserved. Always zero.

Target Abort. This bit signifies that an interrupt has been generated due to the S5935 encountering a target abort

during a PCI bus cycle while the S5935 was the current bus master. This bit operates as read or write one clear. A

write to this bit with the data of “one” will cause this bit to be reset, a write to this bit with the data of “zero” will not

change the state of this bit.

Master Abort. This bit signifies that an interrupt has been generated due to the S5935 encountering a Master Abort

on the PCI bus. A master abort occurs when there is no target response to a PCI bus cycle. This bit operates as

read or write one clear. A write to this bit with the data of “one” will cause this bit be reset, a write to this bit with the

data of “zero” will not change the state of this bit.

Read Transfer Complete. This bit signifies that an interrupt has been generated due to the completion of a PCI bus

master operation involving the transfer of data from the PCI bus to the Add-On. This interrupt will occur when the

Master Read Transfer Count register reaches zero. This bit operates as read or write one clear. A write to this bit

with the data of “one” will cause this bit to be reset; a write to this bit with the data of “zero” will not change the state

of this bit.

Write Transfer Complete. This bit signifies that an interrupt has been generated due to the completion of a PCI bus

master operation involving the transfer of data to the PCI bus from the Add-On. This interrupt will occur when the

Master Write Transfer Count register reaches zero. This bit operates as read or write one clear. A write to this bit

with the data of “one” will cause this bit to be reset; a write to this bit with the data of “zero” will not change the state

of this bit.

Incoming Mailbox Interrupt. This bit is set when the mailbox selected by bits 12 through 8 of this register are written

by the Add-On interface. This bit operates as read or write one clear. A write to this bit with the data of “one” will

cause this bit to be reset; a write to this bit with the data as “zero” will not change the state of this bit.

Outgoing Mailbox Interrupt. This bit is set when the mailbox selected by bits 4 through 0 of this register is read by the

Add-On interface. This bit operates as read or write one clear. A write to this bit with the data of “one” will cause this

bit to be reset; a write to this bit with the data of “zero” will not change the state of this bit.

Interrupt on Read Transfer Complete. This bit enables the occurrence of an interrupt when the read transfer count

reaches zero. This bit is read/write.

Interrupt on Write Transfer Complete. This bit enables the occurrence of an interrupt when the write transfer count

reaches zero. This bit is read/write.

Reserved. Always zero.

Enable incoming mailbox interrupt. This bit allows a write from the incoming mailbox register identified by bits 11

through 8 to produce a PCI interface interrupt. This bit is read/write.

11:10

Incoming Mailbox Interrupt Select. This field selects which of the four incoming mailboxes is to be the source for

causing an incoming mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox 2, [10]b selects mailbox 3 and

[11]b selects mailbox 4. This field is read/write.

9:8

Incoming Mailbox Byte Interrupt select. This field selects which byte of the mailbox selected by bits 10 and 11 above

is to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 1, [10]b selects byte 2, and [11]b selects

byte 3. This field is read/write.

7:5

Reserved, Always zero.

S5935TFC Datasheet(PDF) 70 Page - Applied Micro Circuits Corporation

S5935TFC Datasheet(HTML) 70 Page - Applied Micro Circuits Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL