S5935TFC datasheet(73/204 Pages) AMCC

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S5935 – PCI Product

Revision 1.02 – June 27, 2006

AMCC Confidential and Proprietary

DS1527

Data Book

Table 33. Bus Master Control/Status Register

Bit

Description

31:29

nvRAM Access Control. This field provides a method for access to the optional external non-volatile memory. Write

operations are achieved by a sequence of byte operations involving these bits and the 8-bit field of bits 23 through

16. The sequence requires that the low-order address, high order address, and then a data byte are loaded in order.

Bit 31 of this field acts as a combined enable and ready for the access to the external memory. D31 must be written

to a 1 before an access can begin, and subsequent accesses must wait for bit D31 to become zero (ready).

D31

D30

D29

W/R

Inactive

Load low address byte

Load high address byte

Begin write

Begin read

Ready

Busy

Cautionary note: The nonvolatile memory interface is also available for access by the Add-On interface. Accesses

by both the Add-On and PCI bus to the nv memory are not directly supported by the S5935 device. Software must

be designed to prevent the simultaneous access of nv memory to prevent data corruption within the memory and

provide for accurate data retrieval.

FIFO loop back mode.

Mailbox Flag Reset. Writing a one to this bit causes all mailbox status flags to become reset (EMPTY). It is not nec-

essary to write this bit as zero because it is used internally to produce a reset pulse. Since reading of this bit will

always produce zeros, this bit is write only.

Add-On to PCI FIFO Status Reset. Writing a one to this bit causes the Add-On to PCI (Bus master memory writes)

FIFO empty flag to set indicating empty and the FIFO FULL flag to reset and the FIFO Four Plus word flag to reset.

It is not necessary to write this bit as zero because it is used internally to produce a reset pulse. Since reading of this

bit will always produce zeros, this bit is write only.

PCI to Add-On FIFO Status Reset. Writing a one to this bit causes the PCI to Add-On (Bus master memory reads)

FIFO empty flag to set indicating empty and the FIFO FULL flag to reset and the FIFO Four Plus words available

flag to set. It is not necessary to write this bit as zero because it is used internally to produce a reset pulse. Since

reading of this bit will always produce zeros, this bit is write only.

Add-On pin reset. Writing a one to this bit causes the reset output pin to become active. Writing a zero to this pin is

necessary to remove the assertion of reset. This register bit is read/write.

23:16

Non-volatile memory address/data port. This 8-bit field is used in conjunction with bit 31, 30 and 29 of this register to

access the external non-volatile memory. The contents written are either low address, high address, or data as

defined by bits 30 and 29. This register will contain the external non-volatile memory data when the proper read

sequence for bits 31 through 29 is performed.

Enable memory read multiple during S5935 bus mastering mode.

Read Transfer Enable. This bit must be set to a one for S5935 PCI bus master read transfers to take place. Writing

a zero to this location will suspend an active transfer. An active transfer is one in which the transfer count is not zero.

Read FIFO management scheme. When set to a 1, this bit causes the controller to refrain from requesting the PCI

bus unless it has four or more vacant FIFO locations to fill. Once the controller is granted the PCI bus or is in pos-

session of the bus due to the write channel, this constraint is not meaningful. When this bit is zero the controller will

request the PCI bus if it has at least one vacant FIFO word.

S5935TFC Datasheet(PDF) 73 Page - Applied Micro Circuits Corporation

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